max98091.h

#include "esphome.h"

#define MAX98091_BITS(n, v) \
    (((v) & ((1 << MAX98091_##n##_WIDTH) - 1)) << (MAX98091_##n##_BASE))

#define MAX98091_BOOL(n, v) MAX98091_BITS(n, v ? 1 : 0)
#define MAX98091_ON(n) MAX98091_BOOL(n, true)
#define MAX98091_OFF(n) MAX98091_BOOL(n, false)

#define MAX98091_SYSTEM_CLOCK 0x1B
#define MAX98091_SYSTEM_CLOCK_PSCLK_BASE 4
#define MAX98091_SYSTEM_CLOCK_PSCLK_WIDTH 2

#define SOFTWARE_RESET 0x00

#define JACK_STATUS 0x02
#define JACK_STATUS_JKSNS_BASE 1
#define JACK_STATUS_JKSNS_WIDTH 1
#define JACK_STATUS_LSNS_BASE 2
#define JACK_STATUS_LSNS_WIDTH 1

#define DAI_INTERFACE 0x06

#define DAC_PATH 0x07

#define LINE_TO_ADC 0x09

#define LINE_INPUT_CONFIG 0x0d

#define INPUT_MODE 0x0f

#define MIC1_INPUT_LEVEL 0x10
#define MIC1_INPUT_LEVEL_PGAM1_BASE 0
#define MIC1_INPUT_LEVEL_PGAM1_WIDTH 5
#define MIC1_INPUT_LEVEL_PA1EN_BASE 5
#define MIC1_INPUT_LEVEL_PA1EN_WIDTH 2

#define DIGITAL_MIC_ENABLE 0x13
#define DIGITAL_MIC_ENABLE_DIGMIC1L_BASE 0
#define DIGITAL_MIC_ENABLE_DIGMIC1L_WIDTH 1
#define DIGITAL_MIC_ENABLE_DIGMIC1R_BASE 1
#define DIGITAL_MIC_ENABLE_DIGMIC1R_WIDTH 1
#define DIGITAL_MIC_ENABLE_DIGMIC2L_BASE 2
#define DIGITAL_MIC_ENABLE_DIGMIC2L_WIDTH 1
#define DIGITAL_MIC_ENABLE_DIGMIC2R_BASE 3
#define DIGITAL_MIC_ENABLE_DIGMIC2R_WIDTH 1
#define DIGITAL_MIC_ENABLE_DMICCLK_BASE 4
#define DIGITAL_MIC_ENABLE_DMICCLK_WIDTH 3

#define LEFT_ADC_MIXER 0x15
#define LEFT_ADC_MIXER_LINE_IN_A_BASE 3
#define LEFT_ADC_MIXER_LINE_IN_A_WIDTH 1
#define LEFT_ADC_MIXER_LINE_IN_B_BASE 4
#define LEFT_ADC_MIXER_LINE_IN_B_WIDTH 1
#define LEFT_ADC_MIXER_MICROPHONE_1_BASE 5
#define LEFT_ADC_MIXER_MICROPHONE_1_WIDTH 1

#define RIGHT_ADC_MIXER 0x16
#define RIGHT_ADC_MIXER_LINE_IN_A_BASE 3
#define RIGHT_ADC_MIXER_LINE_IN_A_WIDTH 1
#define RIGHT_ADC_MIXER_LINE_IN_B_BASE 4
#define RIGHT_ADC_MIXER_LINE_IN_B_WIDTH 1
#define RIGHT_ADC_MIXER_MICROPHONE_1_BASE 5
#define RIGHT_ADC_MIXER_MICROPHONE_1_WIDTH 1

#define SYSTEM_CLOCK 0x1B
#define SYSTEM_CLOCK_PSCLK_BASE 4
#define SYSTEM_CLOCK_PSCLK_WIDTH 2

#define IO_CONFIGURATION 0x25

#define FILTER_CONFIGURATION 0x26

#define LEFT_HP_MIXER 0x29
#define LEFT_HP_MIXER_LEFT_DAC_BASE 0
#define LEFT_HP_MIXER_LEFT_DAC_WIDTH 1
#define LEFT_HP_MIXER_RIGHT_DAC_BASE 1
#define LEFT_HP_MIXER_RIGHT_DAC_WIDTH 1
#define LEFT_HP_MIXER_LINE_A_BASE 2
#define LEFT_HP_MIXER_LINE_A_WIDTH 1
#define LEFT_HP_MIXER_LINE_B_BASE 3
#define LEFT_HP_MIXER_LINE_B_WIDTH 1

#define RIGHT_HP_MIXER 0x2A
#define RIGHT_HP_MIXER_LEFT_DAC_BASE 0
#define RIGHT_HP_MIXER_LEFT_DAC_WIDTH 1
#define RIGHT_HP_MIXER_RIGHT_DAC_BASE 1
#define RIGHT_HP_MIXER_RIGHT_DAC_WIDTH 1
#define RIGHT_HP_MIXER_LINE_A_BASE 2
#define RIGHT_HP_MIXER_LINE_A_WIDTH 1
#define RIGHT_HP_MIXER_LINE_B_BASE 3
#define RIGHT_HP_MIXER_LINE_B_WIDTH 1

#define HPCONTROL 0x2B
#define HPCONTROL_MIXHP_LSEL_BASE 4
#define HPCONTROL_MIXHP_LSEL_WIDTH 1
#define HPCONTROL_MIXHP_RSEL_BASE 5
#define HPCONTROL_MIXHP_RSEL_WIDTH 1

#define LEFT_HP_VOLUME 0x2C
#define LEFT_HP_VOLUME_HPVOLL_BASE 0
#define LEFT_HP_VOLUME_HPVOLL_WIDTH 5
#define LEFT_HP_VOLUME_HPLM_BASE 7
#define LEFT_HP_VOLUME_HPLM_WIDTH 1

#define RIGHT_HP_VOLUME 0x2D
#define RIGHT_HP_VOLUME_HPVOLR_BASE 0
#define RIGHT_HP_VOLUME_HPVOLR_WIDTH 5
#define RIGHT_HP_VOLUME_HPRM_BASE 7
#define RIGHT_HP_VOLUME_HPRM_WIDTH 1

#define LEFT_SPK_MIXER 0x2E
#define LEFT_SPK_MIXER_LEFT_DAC_BASE 0
#define LEFT_SPK_MIXER_LEFT_DAC_WIDTH 1
#define LEFT_SPK_MIXER_RIGHT_DAC_BASE 1
#define LEFT_SPK_MIXER_RIGHT_DAC_WIDTH 1
#define LEFT_SPK_MIXER_LINE_A_BASE 2
#define LEFT_SPK_MIXER_LINE_A_WIDTH 1
#define LEFT_SPK_MIXER_LINE_B_BASE 3
#define LEFT_SPK_MIXER_LINE_B_WIDTH 1

#define RIGHT_SPK_MIXER 0x2F
#define RIGHT_SPK_MIXER_LEFT_DAC_BASE 0
#define RIGHT_SPK_MIXER_LEFT_DAC_WIDTH 1
#define RIGHT_SPK_MIXER_RIGHT_DAC_BASE 1
#define RIGHT_SPK_MIXER_RIGHT_DAC_WIDTH 1
#define RIGHT_SPK_MIXER_LINE_A_BASE 2
#define RIGHT_SPK_MIXER_LINE_A_WIDTH 1
#define RIGHT_SPK_MIXER_LINE_B_BASE 3
#define RIGHT_SPK_MIXER_LINE_B_WIDTH 1

#define LEFT_SPK_VOLUME 0x31
#define LEFT_SPK_VOLUME_SPVOLL_BASE 0
#define LEFT_SPK_VOLUME_SPVOLL_WIDTH 6
#define LEFT_SPK_VOLUME_SPLM_BASE 7
#define LEFT_SPK_VOLUME_SPLM_WIDTH 1

#define RIGHT_SPK_VOLUME 0x32
#define RIGHT_SPK_VOLUME_SPVOLR_BASE 0
#define RIGHT_SPK_VOLUME_SPVOLR_WIDTH 6
#define RIGHT_SPK_VOLUME_SPRM_BASE 7
#define RIGHT_SPK_VOLUME_SPRM_WIDTH 1

#define JACK_DETECT 0x3D

#define INPUT_ENABLE 0x3E

#define OUTPUT_ENABLE 0x3F

#define DSP_FILTER_ENABLE 0x41

#define BIAS_CONTROL 0x42

#define DAC_CONTROL 0x43

#define ADC_CONTROL 0x44

#define DEVICE_SHUTDOWN 0x45

#define MAX98091_SOFTWARE_RESET 0x00

#define MAX98091_JACK_STATUS 0x02
#define MAX98091_JACK_STATUS_JKSNS_BASE 1
#define MAX98091_JACK_STATUS_JKSNS_WIDTH 1
#define MAX98091_JACK_STATUS_LSNS_BASE 2
#define MAX98091_JACK_STATUS_LSNS_WIDTH 1

#define MAX98091_DAI_INTERFACE 0x06

#define MAX98091_DAC_PATH 0x07

#define MAX98091_LINE_TO_ADC 0x09

#define MAX98091_LINE_INPUT_CONFIG 0x0d

#define MAX98091_INPUT_MODE 0x0f

#define MAX98091_MIC1_INPUT_LEVEL 0x10
#define MAX98091_MIC1_INPUT_LEVEL_PGAM1_BASE 0
#define MAX98091_MIC1_INPUT_LEVEL_PGAM1_WIDTH 5
#define MAX98091_MIC1_INPUT_LEVEL_PA1EN_BASE 5
#define MAX98091_MIC1_INPUT_LEVEL_PA1EN_WIDTH 2

#define MAX98091_DIGITAL_MIC_ENABLE 0x13
#define MAX98091_DIGITAL_MIC_ENABLE_DIGMIC1L_BASE 0
#define MAX98091_DIGITAL_MIC_ENABLE_DIGMIC1L_WIDTH 1
#define MAX98091_DIGITAL_MIC_ENABLE_DIGMIC1R_BASE 1
#define MAX98091_DIGITAL_MIC_ENABLE_DIGMIC1R_WIDTH 1
#define MAX98091_DIGITAL_MIC_ENABLE_DIGMIC2L_BASE 2
#define MAX98091_DIGITAL_MIC_ENABLE_DIGMIC2L_WIDTH 1
#define MAX98091_DIGITAL_MIC_ENABLE_DIGMIC2R_BASE 3
#define MAX98091_DIGITAL_MIC_ENABLE_DIGMIC2R_WIDTH 1
#define MAX98091_DIGITAL_MIC_ENABLE_DMICCLK_BASE 4
#define MAX98091_DIGITAL_MIC_ENABLE_DMICCLK_WIDTH 3

#define MAX98091_LEFT_ADC_MIXER 0x15
#define MAX98091_LEFT_ADC_MIXER_LINE_IN_A_BASE 3
#define MAX98091_LEFT_ADC_MIXER_LINE_IN_A_WIDTH 1
#define MAX98091_LEFT_ADC_MIXER_LINE_IN_B_BASE 4
#define MAX98091_LEFT_ADC_MIXER_LINE_IN_B_WIDTH 1
#define MAX98091_LEFT_ADC_MIXER_MICROPHONE_1_BASE 5
#define MAX98091_LEFT_ADC_MIXER_MICROPHONE_1_WIDTH 1

#define MAX98091_RIGHT_ADC_MIXER 0x16
#define MAX98091_RIGHT_ADC_MIXER_LINE_IN_A_BASE 3
#define MAX98091_RIGHT_ADC_MIXER_LINE_IN_A_WIDTH 1
#define MAX98091_RIGHT_ADC_MIXER_LINE_IN_B_BASE 4
#define MAX98091_RIGHT_ADC_MIXER_LINE_IN_B_WIDTH 1
#define MAX98091_RIGHT_ADC_MIXER_MICROPHONE_1_BASE 5
#define MAX98091_RIGHT_ADC_MIXER_MICROPHONE_1_WIDTH 1

#define MAX98091_SYSTEM_CLOCK 0x1B
#define MAX98091_SYSTEM_CLOCK_PSCLK_BASE 4
#define MAX98091_SYSTEM_CLOCK_PSCLK_WIDTH 2

#define MAX98091_IO_CONFIGURATION 0x25

#define MAX98091_FILTER_CONFIGURATION 0x26

#define MAX98091_LEFT_HP_MIXER 0x29
#define MAX98091_LEFT_HP_MIXER_LEFT_DAC_BASE 0
#define MAX98091_LEFT_HP_MIXER_LEFT_DAC_WIDTH 1
#define MAX98091_LEFT_HP_MIXER_RIGHT_DAC_BASE 1
#define MAX98091_LEFT_HP_MIXER_RIGHT_DAC_WIDTH 1
#define MAX98091_LEFT_HP_MIXER_LINE_A_BASE 2
#define MAX98091_LEFT_HP_MIXER_LINE_A_WIDTH 1
#define MAX98091_LEFT_HP_MIXER_LINE_B_BASE 3
#define MAX98091_LEFT_HP_MIXER_LINE_B_WIDTH 1

#define MAX98091_RIGHT_HP_MIXER 0x2A
#define MAX98091_RIGHT_HP_MIXER_LEFT_DAC_BASE 0
#define MAX98091_RIGHT_HP_MIXER_LEFT_DAC_WIDTH 1
#define MAX98091_RIGHT_HP_MIXER_RIGHT_DAC_BASE 1
#define MAX98091_RIGHT_HP_MIXER_RIGHT_DAC_WIDTH 1
#define MAX98091_RIGHT_HP_MIXER_LINE_A_BASE 2
#define MAX98091_RIGHT_HP_MIXER_LINE_A_WIDTH 1
#define MAX98091_RIGHT_HP_MIXER_LINE_B_BASE 3
#define MAX98091_RIGHT_HP_MIXER_LINE_B_WIDTH 1

#define MAX98091_HPCONTROL 0x2B
#define MAX98091_HPCONTROL_MIXHP_LSEL_BASE 4
#define MAX98091_HPCONTROL_MIXHP_LSEL_WIDTH 1
#define MAX98091_HPCONTROL_MIXHP_RSEL_BASE 5
#define MAX98091_HPCONTROL_MIXHP_RSEL_WIDTH 1

#define MAX98091_LEFT_HP_VOLUME 0x2C
#define MAX98091_LEFT_HP_VOLUME_HPVOLL_BASE 0
#define MAX98091_LEFT_HP_VOLUME_HPVOLL_WIDTH 5
#define MAX98091_LEFT_HP_VOLUME_HPLM_BASE 7
#define MAX98091_LEFT_HP_VOLUME_HPLM_WIDTH 1

#define MAX98091_RIGHT_HP_VOLUME 0x2D
#define MAX98091_RIGHT_HP_VOLUME_HPVOLR_BASE 0
#define MAX98091_RIGHT_HP_VOLUME_HPVOLR_WIDTH 5
#define MAX98091_RIGHT_HP_VOLUME_HPRM_BASE 7
#define MAX98091_RIGHT_HP_VOLUME_HPRM_WIDTH 1

#define MAX98091_LEFT_SPK_MIXER 0x2E
#define MAX98091_LEFT_SPK_MIXER_LEFT_DAC_BASE 0
#define MAX98091_LEFT_SPK_MIXER_LEFT_DAC_WIDTH 1
#define MAX98091_LEFT_SPK_MIXER_RIGHT_DAC_BASE 1
#define MAX98091_LEFT_SPK_MIXER_RIGHT_DAC_WIDTH 1
#define MAX98091_LEFT_SPK_MIXER_LINE_A_BASE 2
#define MAX98091_LEFT_SPK_MIXER_LINE_A_WIDTH 1
#define MAX98091_LEFT_SPK_MIXER_LINE_B_BASE 3
#define MAX98091_LEFT_SPK_MIXER_LINE_B_WIDTH 1

#define MAX98091_RIGHT_SPK_MIXER 0x2F
#define MAX98091_RIGHT_SPK_MIXER_LEFT_DAC_BASE 0
#define MAX98091_RIGHT_SPK_MIXER_LEFT_DAC_WIDTH 1
#define MAX98091_RIGHT_SPK_MIXER_RIGHT_DAC_BASE 1
#define MAX98091_RIGHT_SPK_MIXER_RIGHT_DAC_WIDTH 1
#define MAX98091_RIGHT_SPK_MIXER_LINE_A_BASE 2
#define MAX98091_RIGHT_SPK_MIXER_LINE_A_WIDTH 1
#define MAX98091_RIGHT_SPK_MIXER_LINE_B_BASE 3
#define MAX98091_RIGHT_SPK_MIXER_LINE_B_WIDTH 1

#define MAX98091_LEFT_SPK_VOLUME 0x31
#define MAX98091_LEFT_SPK_VOLUME_SPVOLL_BASE 0
#define MAX98091_LEFT_SPK_VOLUME_SPVOLL_WIDTH 6
#define MAX98091_LEFT_SPK_VOLUME_SPLM_BASE 7
#define MAX98091_LEFT_SPK_VOLUME_SPLM_WIDTH 1

#define MAX98091_RIGHT_SPK_VOLUME 0x32
#define MAX98091_RIGHT_SPK_VOLUME_SPVOLR_BASE 0
#define MAX98091_RIGHT_SPK_VOLUME_SPVOLR_WIDTH 6
#define MAX98091_RIGHT_SPK_VOLUME_SPRM_BASE 7
#define MAX98091_RIGHT_SPK_VOLUME_SPRM_WIDTH 1

#define MAX98091_JACK_DETECT 0x3D

#define MAX98091_INPUT_ENABLE 0x3E

#define MAX98091_OUTPUT_ENABLE 0x3F

#define MAX98091_DSP_FILTER_ENABLE 0x41

#define MAX98091_BIAS_CONTROL 0x42

#define MAX98091_DAC_CONTROL 0x43

#define MAX98091_ADC_CONTROL 0x44

#define MAX98091_DEVICE_SHUTDOWN 0x45

class MAX98091 : public PollingComponent, public BinarySensor {
 public:
  MAX98091() : PollingComponent(300) {}
  float get_setup_priority() const override { return esphome::setup_priority::LATE; }

  void write_cmd(uint8_t reg, uint8_t cmd) {
    Wire.beginTransmission(0x10);
    Wire.write(reg);
    Wire.write(cmd);
    Wire.endTransmission();
  }

  void setup() override {
    Wire.begin();
    write_cmd(SOFTWARE_RESET, 0x80);
    write_cmd(DEVICE_SHUTDOWN, 0);
    // pclk = mclk / 1
    write_cmd(SYSTEM_CLOCK, MAX98091_BITS(SYSTEM_CLOCK_PSCLK, 1));
    // music, dc filter in record and playback
    write_cmd(FILTER_CONFIGURATION, (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
    // Sets up DAI for left-justified slave mode operation.
    write_cmd(DAI_INTERFACE, 1 << 2);
    // Sets up the DAC to speaker path
    write_cmd(DAC_PATH, 1 << 5);
    // Somehow this was needed to get an input signal to the ADC, even though
    // all other registers should be taken care of later. Don't know why.
    // Sets up the line in to adc path
    write_cmd(LINE_TO_ADC, 1 << 6);
    // SDOUT, SDIN enabled
    write_cmd(IO_CONFIGURATION, (1 << 1) | (1 << 0));
    // bandgap bias
    write_cmd(BIAS_CONTROL, 1 << 0);
    // high performane mode
    write_cmd(DAC_CONTROL, 1 << 0);
    // enable micbias, line input amps, ADCs
    write_cmd(INPUT_ENABLE, (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
    // IN3 SE -> Line A, IN4 SE -> Line B
    write_cmd(LINE_INPUT_CONFIG, (1 << 3) | (1 << 2));
    // 64x oversampling, dithering, high performance ADC
    write_cmd(ADC_CONTROL, (1 << 1) | (1 << 0));
    write_cmd(DIGITAL_MIC_ENABLE, 0);
    // IN5/IN6 to MIC1
    write_cmd(INPUT_MODE, (1 << 0));

    write_cmd(LEFT_SPK_MIXER,
                   MAX98091_BOOL(LEFT_SPK_MIXER_LINE_A, false) |
                       MAX98091_ON(LEFT_SPK_MIXER_LEFT_DAC));
    write_cmd(RIGHT_SPK_MIXER,
                   MAX98091_BOOL(RIGHT_SPK_MIXER_LINE_B, false) |
                       MAX98091_ON(RIGHT_SPK_MIXER_RIGHT_DAC));

    write_cmd(MAX98091_LEFT_ADC_MIXER, 0);
    write_cmd(MAX98091_RIGHT_ADC_MIXER, 0);
/*
    flow3r_bsp_max98091_line_in_set_hardware_thru(0);
    flow3r_bsp_max98091_headset_set_gain_dB(0);
    flow3r_bsp_max98091_input_set_source(flow3r_bsp_audio_input_source_none);
*/
    // output enable: enable dacs
    write_cmd(OUTPUT_ENABLE, (1 << 1) | (1 << 0));
    // power up
    write_cmd(DEVICE_SHUTDOWN, 1 << 7);
    // enable outputs, dacs
    write_cmd(OUTPUT_ENABLE, (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0));
    // disable all digital filters except for dc blocking
    write_cmd(DSP_FILTER_ENABLE, 0x0);
    // jack detect enable
    write_cmd(JACK_DETECT, 1 << 7);
    ESP_LOGD("MAX98091", "Init done...");

    write_cmd(MAX98091_LEFT_SPK_VOLUME,
              MAX98091_BOOL(LEFT_SPK_VOLUME_SPLM, false) |
              MAX98091_BITS(LEFT_SPK_VOLUME_SPVOLL, 0x2C));
    write_cmd(MAX98091_RIGHT_SPK_VOLUME,
              MAX98091_BOOL(RIGHT_SPK_VOLUME_SPRM, false) |
              MAX98091_BITS(RIGHT_SPK_VOLUME_SPVOLR, 0x2C));
  }

  void update() override {
    publish_state(true);
  }
};