From 02ca13ab756c5fd21001a54b21ce54feea83d3a4 Mon Sep 17 00:00:00 2001
From: David Sawatzke <david-sawatzke@users.noreply.github.com>
Date: Tue, 1 Jan 2019 18:33:23 +0100
Subject: [PATCH] Have pin bindings as subsets of families

---
 src/pin_mappings.rs | 133 ++++++++++++++++++++++++--------------------
 1 file changed, 73 insertions(+), 60 deletions(-)

diff --git a/src/pin_mappings.rs b/src/pin_mappings.rs
index 0858775..900b8c2 100644
--- a/src/pin_mappings.rs
+++ b/src/pin_mappings.rs
@@ -52,16 +52,16 @@ pins! {
     PB9 => {AF1: SdaPin<I2C1>}
 }
 
-#[cfg(any(feature = "stm32f030", feature = "stm32f042"))]
-pins! {
-    PA11 => {AF5: SclPin<I2C1>},
-    PA12 => {AF5: SdaPin<I2C1>}
-}
-
-#[cfg(any(feature = "stm32f030", feature = "stm32f070"))]
+#[cfg(feature = "stm32f030")]
 pins! {
     PA0 => {AF4: TxPin<USART4>},
     PA1 => {AF4: RxPin<USART4>},
+    PA4 => {AF5: TxPin<USART6>},
+    PA5 => {AF5: RxPin<USART6>},
+    PA11 => {AF5: SclPin<I2C1>},
+    PA12 => {AF5: SdaPin<I2C1>},
+    PB3 => {AF4: TxPin<USART5>},
+    PB4 => {AF4: RxPin<USART5>},
     PB10 => {
         AF4: TxPin<USART3>,
         AF5: SckPin<SPI2>
@@ -79,14 +79,6 @@ pins! {
         AF0: RxPin<USART4>,
         AF1: RxPin<USART3>
     }
-}
-
-#[cfg(feature = "stm32f030")]
-pins! {
-    PA4 => {AF5: TxPin<USART6>},
-    PA5 => {AF5: RxPin<USART6>},
-    PB3 => {AF4: TxPin<USART5>},
-    PB4 => {AF4: RxPin<USART5>},
     PC0 => {AF2: TxPin<USART6>},
     PC1 => {AF2: RxPin<USART6>},
     PC12 => {AF2: RxPin<USART5>},
@@ -97,78 +89,99 @@ pins! {
 pins! {
     PA2 => {AF1: TxPin<USART1>},
     PA3 => {AF1: RxPin<USART1>},
+    PA9 => {AF4: SclPin<I2C1>},
+    PA10 => {AF4: SdaPin<I2C1>},
     PA14 => {AF1: TxPin<USART1>},
     PA15 => {AF1: RxPin<USART1>},
+    PB10 => {AF1: SclPin<I2C1>},
+    PB11 => {AF1: SdaPin<I2C1>},
     PB13 => {AF0: SckPin<SPI1>},
     PB14 => {AF0: MisoPin<SPI1>},
     PB15 => {AF0: MosiPin<SPI1>}
 }
 
-#[cfg(any(
-    feature = "stm32f030x8",
-    feature = "stm32f030xc",
-    feature = "stm32f042",
-    feature = "stm32f070",
-))]
+#[cfg(any(feature = "stm32f030x8", feature = "stm32f030xc"))]
 pins! {
     PA2 => {AF1: TxPin<USART2>},
     PA3 => {AF1: RxPin<USART2>},
     PA14 => {AF1: TxPin<USART2>},
-    PA15 => {AF1: RxPin<USART2>}
-}
-#[cfg(any(
-    feature = "stm32f030x8",
-    feature = "stm32f030xc",
-    feature = "stm32f070xb"
-))]
-pins! {
+    PA15 => {AF1: RxPin<USART2>},
+    PB10 => {AF1: SclPin<I2C2>},
+    PB11 => {AF1: SdaPin<I2C1>},
     PB13 => {AF0: SckPin<SPI2>},
     PB14 => {AF0: MisoPin<SPI2>},
     PB15 => {AF0: MosiPin<SPI2>}
 }
 
-#[cfg(any(
-    feature = "stm32f030x6",
-    feature = "stm32f030xc",
-    feature = "stm32f042",
-    feature = "stm32f070x6"
-))]
+#[cfg(any(feature = "stm32f030xc",))]
 pins! {
     PA9 => {AF4: SclPin<I2C1>},
-    PA10 => {AF4: SdaPin<I2C1>}
+    PA10 => {AF4: SdaPin<I2C1>},
+    PB13 => {AF5: SclPin<I2C1>},
+    PB14 => {AF5: SdaPin<I2C1>},
+    PF0 => {AF1: SdaPin<I2C1>},
+    PF1 => {AF1: SclPin<I2C1>}
 }
 
-#[cfg(any(
-    feature = "stm32f030x6",
-    feature = "stm32f042",
-    feature = "stm32f070xb"
-))]
+#[cfg(feature = "stm32f042")]
 pins! {
+    PA11 => {AF5: SclPin<I2C1>},
+    PA12 => {AF5: SdaPin<I2C1>},
+    PA2 => {AF1: TxPin<USART2>},
+    PA3 => {AF1: RxPin<USART2>},
+    PA9 => {AF4: SclPin<I2C1>},
+    PA10 => {AF4: SdaPin<I2C1>},
+    PA14 => {AF1: TxPin<USART2>},
+    PA15 => {AF1: RxPin<USART2>},
     PB10 => {AF1: SclPin<I2C1>},
-    PB11 => {AF1: SdaPin<I2C1>}
+    PB11 => {AF1: SdaPin<I2C1>},
+    PB13 => {AF5: SclPin<I2C1>},
+    PB14 => {AF5: SdaPin<I2C1>},
+    PF0 => {AF1: SdaPin<I2C1>},
+    PF1 => {AF1: SclPin<I2C1>}
 }
 
-#[cfg(any(feature = "stm32f030x8", feature = "stm32f030xc"))]
+#[cfg(feature = "stm32f070")]
 pins! {
-    PB10 => {AF1: SclPin<I2C2>},
-    PB11 => {AF1: SdaPin<I2C1>}
-}
-#[cfg(any(
-    feature = "stm32f042",
-    feature = "stm32f030xc",
-    feature = "stm32f070x6",
-))]
-pins! {
-    PF0 => {AF1: SdaPin<I2C1>}
-    PF1 => {AF1: SclPin<I2C1>},
+    PA0 => {AF4: TxPin<USART4>},
+    PA1 => {AF4: RxPin<USART4>},
+    PA2 => {AF1: TxPin<USART2>},
+    PA3 => {AF1: RxPin<USART2>},
+    PA14 => {AF1: TxPin<USART2>},
+    PA15 => {AF1: RxPin<USART2>},
+    PB10 => {
+        AF4: TxPin<USART3>,
+        AF5: SckPin<SPI2>
+    },
+    PB11 => {AF4: RxPin<USART3>},
+    PC2 => {AF1: MisoPin<SPI2>},
+    PC3 => {AF1: MosiPin<SPI2>},
+    PC4 => {AF1: TxPin<USART3>},
+    PC5 => {AF1: RxPin<USART3>},
+    PC10 => {
+        AF0: TxPin<USART4>,
+        AF1: TxPin<USART3>
+    },
+    PC11 => {
+        AF0: RxPin<USART4>,
+        AF1: RxPin<USART3>
+    }
 }
 
-#[cfg(any(
-    feature = "stm32f042",
-    feature = "stm32f030xc",
-    feature = "stm32f070xb"
-))]
+#[cfg(feature = "stm32f070xb")]
 pins! {
+    PB10 => {AF1: SclPin<I2C1>},
+    PB11 => {AF1: SdaPin<I2C1>},
+    PB13 => {AF0: SckPin<SPI2>},
+    PB14 => {AF0: MisoPin<SPI2>},
     PB13 => {AF5: SclPin<I2C1>},
-    PB14 => {AF5: SdaPin<I2C1>}
+    PB14 => {AF5: SdaPin<I2C1>},
+    PB15 => {AF0: MosiPin<SPI2>}
+}
+#[cfg(feature = "stm32f070x6")]
+pins! {
+    PA9 => {AF4: SclPin<I2C1>},
+    PA10 => {AF4: SdaPin<I2C1>},
+    PF0 => {AF1: SdaPin<I2C1>},
+    PF1 => {AF1: SclPin<I2C1>}
 }