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regression in ethernet DMA initialization for H743 chips #448
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I can confirm that Stabilizer's hardware-in-the-loop tests indicate that networking no longer functions on the H743 chips with the latest hal rev |
I can reproduce this on two development boards:
For me the symptom is that the PHY never reports the link is up (over the MDIO interface) and the board does not respond to pings. Reverting the change to Why the change in #445 is required for the NUCLEO-H723ZG but fails on the STM32H735G-DK is really not clear. Those STM32 part share a reference manual, so I would expect them to both work with the same initialisation sequence. Perhaps either the board power configuration (LDO vs SMPS) or PHY configuration is to blame. In the meantime I would propose reverting the change to |
I'm on board with your assessment @richardeoin - I didn't see a thorough explanation in #445 why it was required outside of "Seems to work now". If that truly is the case, we can device gate it, but feels like more investigation is required. |
Reading #445 more carefully I see it says "either order works on the nucleo board". The change is not required for the NUCLEO board, only for some custom hardware with a H723. I suspect the difference there is not the H723 vs other H7 parts, but the PHY configuration in that custom hardware. So by reverting the change we get a configuration that works with all the NUCLEO/DISCO boards we know of, and all but one of the custom hardware items. I think that's the right choice. |
One of the changes merged in by #445 moves the write to the ETH_DMAMR register to before the ethernet peripheral clocks are enabled
https://github.com/stm32-rs/stm32h7xx-hal/pull/445/files#diff-bc6d950ee1ed8e0df070d5ac2e9190dea3730fc251d9ca1b3c9bdad8c7f0bd3aR458-L478
This breaks the ethernet DMA initialization on my STM32H743IIT6
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