From 7b1e75ce83a5ca1bbe7f26e2cf00dc0d6bd95e7d Mon Sep 17 00:00:00 2001 From: Kriyszig Date: Tue, 16 Jul 2019 01:21:06 +0530 Subject: [PATCH] Editorial: Fixed typo in Shared Memory Guidelines note (#1631) architectrue -> architecture --- spec.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spec.html b/spec.html index 7891a7dc1e..2c1c9df2f4 100644 --- a/spec.html +++ b/spec.html @@ -39701,7 +39701,7 @@

Shared Memory Guidelines

The following are guidelines for ECMAScript implementers generating machine code for shared memory accesses.

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For architectures with memory models no weaker than those of ARM or Power, non-atomic stores and loads may be compiled to bare stores and loads on the target architecture. Atomic stores and loads may be compiled down to instructions that guarantee sequential consistency. If no such instructions exist, memory barriers are to be employed, such as placing barriers on both sides of a bare store or load. Read-modify-write operations may be compiled to read-modify-write instructions on the target architectrue, such as LOCK-prefixed instructions on x86, load-exclusive/store-exclusive instructions on ARM, and load-link/store-conditional instructions on Power.

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For architectures with memory models no weaker than those of ARM or Power, non-atomic stores and loads may be compiled to bare stores and loads on the target architecture. Atomic stores and loads may be compiled down to instructions that guarantee sequential consistency. If no such instructions exist, memory barriers are to be employed, such as placing barriers on both sides of a bare store or load. Read-modify-write operations may be compiled to read-modify-write instructions on the target architecture, such as LOCK-prefixed instructions on x86, load-exclusive/store-exclusive instructions on ARM, and load-link/store-conditional instructions on Power.

Specifically, the memory model is intended to allow code generation as follows.