forked from xCuri0/ReBarUEFI
-
Notifications
You must be signed in to change notification settings - Fork 12
/
Copy pathSetupNvStraps.c
343 lines (265 loc) · 14.2 KB
/
SetupNvStraps.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
#include <stdbool.h>
#include <stdint.h>
#include <Uefi.h>
#include <Guid/EventGroup.h>
#include <Protocol/S3SaveState.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DxeServicesTableLib.h>
#include <IndustryStandard/Pci.h>
#include "StatusVar.h"
#include "PciConfig.h"
#include "S3ResumeScript.h"
#include "DeviceRegistry.h"
#include "NvStrapsConfig.h"
#include "ReBar.h"
#include "SetupNvStraps.h"
// From envytools documentation at:
// https://envytools.readthedocs.io/en/latest/hw/io/pstraps.html
static uint_least32_t const
TARGET_GPU_STRAPS_BASE_OFFSET = 0x0010'1000u,
TARGET_GPU_STRAPS_SET0_OFFSET = 0x0000'0000u,
TARGET_GPU_STRAPS_SET1_OFFSET = 0x0000'000Cu,
BAR1_SIZE_PART1_SHIFT = 14u,
BAR1_SIZE_PART1_BITSIZE = 2u,
BAR1_SIZE_PART2_SHIFT = 20u,
BAR1_SIZE_PART2_BITSIZE = 3u;
static uint_least16_t enumeratedBridges[ARRAY_SIZE(config->bridge)] = { 0, };
static uint_least8_t enumeratedBridgeCount = 0u;
static bool isBridgeEnumerated(uint_least16_t pciLocation)
{
for (unsigned index = 0u; index < enumeratedBridgeCount; index++)
if (enumeratedBridges[index] == pciLocation)
return true;
return false;
}
void NvStraps_EnumDevice(UINTN pciAddress, uint_least16_t vendorId, uint_least16_t deviceId, uint_least8_t headerType)
{
if (pciIsPciBridge(headerType) && (enumeratedBridgeCount < ARRAY_SIZE(enumeratedBridges)))
{
uint_least8_t bus, dev, fun;
pciUnpackAddress(pciAddress, &bus, &dev, &fun);
if (NvStrapsConfig_HasBridgeDevice(config, bus, dev, fun) != ((uint_least32_t)WORD_BITMASK << WORD_BITSIZE | WORD_BITMASK))
{
enumeratedBridges[enumeratedBridgeCount++] = pciPackLocation(bus, dev, fun);
SetStatusVar(StatusVar_BridgeFound);
}
}
}
bool NvStraps_CheckDevice(UINTN pciAddress, uint_least16_t vendorId, uint_least16_t deviceId, uint_least16_t *subsysVenID, uint_least16_t *subsysDevID)
{
if (vendorId == TARGET_GPU_VENDOR_ID && NvStrapsConfig_IsGpuConfigured(config) && pciIsVgaController(pciDeviceClass(pciAddress)))
{
EFI_STATUS status = pciReadDeviceSubsystem(pciAddress, subsysVenID, subsysDevID);
if (EFI_ERROR(status))
return SetEFIError(EFIError_PCI_DeviceSubsystem, status), false;
uint_least8_t bus, device, fun;
pciUnpackAddress(pciAddress, &bus, &device, &fun);
NvStraps_BarSize barSizeSelector =
NvStrapsConfig_LookupBarSize(config, deviceId, *subsysVenID, *subsysDevID, bus, device, fun);
if (barSizeSelector.priority == UNCONFIGURED || barSizeSelector.barSizeSelector == BarSizeSelector_None || barSizeSelector.barSizeSelector == BarSizeSelector_Excluded)
{
SetDeviceStatusVar(pciAddress, barSizeSelector.barSizeSelector == BarSizeSelector_Excluded ? StatusVar_GpuExcluded : StatusVar_GPU_Unconfigured);
return false;
}
SetDeviceStatusVar(pciAddress, StatusVar_GpuFound);
return true;
}
return false;
}
static bool ConfigureNvStrapsBAR1Size(EFI_PHYSICAL_ADDRESS baseAddress0, UINT8 barSize)
{
UINT32
*pSTRAPS0 = (UINT32 *)(baseAddress0 + TARGET_GPU_STRAPS_BASE_OFFSET + TARGET_GPU_STRAPS_SET0_OFFSET),
*pSTRAPS1 = (UINT32 *)(baseAddress0 + TARGET_GPU_STRAPS_BASE_OFFSET + TARGET_GPU_STRAPS_SET1_OFFSET),
STRAPS0, STRAPS1;
CopyMem(&STRAPS0, pSTRAPS0, sizeof STRAPS0);
CopyMem(&STRAPS1, pSTRAPS1, sizeof STRAPS1);
UINT8
barSize_Part1 = STRAPS0 >> BAR1_SIZE_PART1_SHIFT & (UINT32_C(1) << BAR1_SIZE_PART1_BITSIZE) - 1u,
barSize_Part2 = STRAPS1 >> BAR1_SIZE_PART2_SHIFT & (UINT32_C(1) << BAR1_SIZE_PART2_BITSIZE) - 1u;
UINT8
targetBarSize_Part1 = barSize < 3u ? barSize : barSize < 10u ? 2u : 3u,
targetBarSize_Part2 = barSize < 3u ? 0u : barSize < 10u ? barSize - 2u : 7u;
if (barSize_Part1 != targetBarSize_Part1)
{
STRAPS0 &= ~(UINT32)(((UINT32_C(1) << BAR1_SIZE_PART1_BITSIZE) - 1u) << BAR1_SIZE_PART1_SHIFT);
STRAPS0 |= (UINT32)targetBarSize_Part1 << BAR1_SIZE_PART1_SHIFT;
STRAPS0 |= UINT32_C(1) << (DWORD_SIZE * BYTE_BITSIZE - 1u);
CopyMem(pSTRAPS0, &STRAPS0, sizeof STRAPS0);
EFI_STATUS status = S3ResumeScript_MemReadWrite_DWORD
(
(UINT64)baseAddress0 + TARGET_GPU_STRAPS_BASE_OFFSET + TARGET_GPU_STRAPS_SET0_OFFSET,
(UINT32)targetBarSize_Part1 << BAR1_SIZE_PART1_SHIFT | UINT32_C(1) << (DWORD_SIZE * BYTE_BITSIZE - 1u),
(UINT32) ~(UINT32)(((UINT32_C(1) << BAR1_SIZE_PART1_BITSIZE) - 1u) << BAR1_SIZE_PART1_SHIFT)
);
if (EFI_ERROR(status))
SetEFIError(EFIError_WriteS3SaveStateProtocol, status);
}
if (barSize_Part2 != targetBarSize_Part2)
{
STRAPS1 &= ~(UINT32)(((UINT32_C(1) << BAR1_SIZE_PART2_BITSIZE) - 1u) << BAR1_SIZE_PART2_SHIFT);
STRAPS1 |= (UINT32)targetBarSize_Part2 << BAR1_SIZE_PART2_SHIFT;
STRAPS1 |= UINT32_C(1) << (DWORD_SIZE * BYTE_BITSIZE - 1u);
CopyMem(pSTRAPS1, &STRAPS1, sizeof STRAPS1);
EFI_STATUS status = S3ResumeScript_MemReadWrite_DWORD
(
(UINT64)baseAddress0 + TARGET_GPU_STRAPS_BASE_OFFSET + TARGET_GPU_STRAPS_SET1_OFFSET,
(UINT32)targetBarSize_Part2 << BAR1_SIZE_PART2_SHIFT | UINT32_C(1) << (DWORD_SIZE * BYTE_BITSIZE - 1u),
(UINT32) ~(UINT32)(((UINT32_C(1) << BAR1_SIZE_PART2_BITSIZE) - 1u) << BAR1_SIZE_PART2_SHIFT)
);
if (EFI_ERROR(status))
SetEFIError(EFIError_WriteS3SaveStateProtocol, status);
}
return barSize_Part1 + barSize_Part2 != targetBarSize_Part1 + targetBarSize_Part2;
}
void NvStraps_Setup(UINTN pciAddress, uint_least16_t vendorId, uint_least16_t deviceId, uint_least16_t subsysVenID, uint_least16_t subsysDevID, uint_fast8_t nPciBarSizeSelector)
{
uint_least8_t bus, device, func;
pciUnpackAddress(pciAddress, &bus, &device, &func);
NvStraps_BarSize barSizeSelector =
NvStrapsConfig_LookupBarSize(config, deviceId, subsysVenID, subsysDevID, bus, device, func);
if (barSizeSelector.priority == UNCONFIGURED || barSizeSelector.barSizeSelector == BarSizeSelector_None || barSizeSelector.barSizeSelector == BarSizeSelector_Excluded)
return;
NvStraps_BarSizeMaskOverride sizeMaskOverride = NvStrapsConfig_LookupBarSizeMaskOverride(config, deviceId, subsysVenID, subsysDevID, bus, device, func);
NvStraps_GPUConfig const *gpuConfig = NvStrapsConfig_LookupGPUConfig(config, bus, device, func);
if (!gpuConfig)
{
SetDeviceStatusVar(pciAddress, StatusVar_NoGpuConfig);
return;
}
if (gpuConfig->bar0.base >= UINT32_MAX || gpuConfig->bar0.top >= UINT32_MAX || gpuConfig->bar0.base & UINT32_C(0x0000'000F)
|| gpuConfig->bar0.base % (gpuConfig->bar0.top - gpuConfig->bar0.base + 1u))
{
SetDeviceStatusVar(pciAddress, StatusVar_BadGpuConfig);
return;
}
NvStraps_BridgeConfig const *bridgeConfig = NvStrapsConfig_LookupBridgeConfig(config, bus);
if (!bridgeConfig)
{
SetDeviceStatusVar(pciAddress, StatusVar_NoBridgeConfig);
return;
}
else
if (!isBridgeEnumerated(pciPackLocation(bridgeConfig->bridgeBus, bridgeConfig->bridgeDevice, bridgeConfig->bridgeFunction)))
{
SetDeviceStatusVar(pciAddress, StatusVar_BridgeNotEnumerated);
return;
}
UINTN bridgePciAddress = EFI_PCI_ADDRESS(bridgeConfig->bridgeBus, bridgeConfig->bridgeDevice, bridgeConfig->bridgeFunction, 0u);
uint_least8_t bridgeSecondaryBus;
EFI_STATUS status = pciBridgeSecondaryBus(bridgePciAddress, &bridgeSecondaryBus);
if (EFI_ERROR(status))
{
SetDeviceEFIError(pciAddress, EFIError_PCI_BridgeSecondaryBus, status);
return;
}
if (bridgeSecondaryBus != bus)
{
SetDeviceStatusVar(pciAddress, StatusVar_BadBridgeConfig);
return;
}
UINT32 bridgeSaveArea[3u], gpuSaveArea[2u];
// EFI_PHYSICAL_ADDRESS baseAddress0 = BASE_4GB - 1u, bridgeIoPortRangeBegin = BASE_64KB - 1u;
// if (EFI_SUCCESS == gDS->AllocateMemorySpace(EfiGcdAllocateMaxAddressSearchTopDown, EfiGcdMemoryTypeMemoryMappedIo, 25u, SIZE_32MB, &baseAddress0, reBarImageHandle, NULL))
// {
// if (EFI_SUCCESS == gDS->AllocateIoSpace(EfiGcdAllocateMaxAddressSearchTopDown, EfiGcdIoTypeIo, 12u, SIZE_1KB / 2, &bridgeIoPortRangeBegin, reBarImageHandle, NULL))
// {
// EFI_GCD_MEMORY_SPACE_DESCRIPTOR memoryDescriptor;
//
// if (EFI_ERROR(gDS->GetMemorySpaceDescriptor(baseAddress0, &memoryDescriptor)))
// SetStatusVar(StatusVar_EFIError);
// else
// if (EFI_ERROR(gDS->SetMemorySpaceAttributes(baseAddress0, SIZE_16MB, memoryDescriptor.Attributes | EFI_MEMORY_UC)))
// SetStatusVar(StatusVar_EFIError);
pciSaveAndRemapBridgeConfig(bridgePciAddress, bridgeSaveArea, gpuConfig->bar0.base, gpuConfig->bar0.top, TARGET_BRIDGE_IO_BASE_LIMIT);
pciSaveAndRemapDeviceBAR0(pciAddress, gpuSaveArea, gpuConfig->bar0.base);
bool configUpdated = ConfigureNvStrapsBAR1Size(gpuConfig->bar0.base & UINT32_C(0xFFFF'FFF0), barSizeSelector.barSizeSelector); // mask the flag bits from the address
// RecordUpdateGPU(bus, device, func, barSizeSelector.barSizeSelector);
pciRestoreDeviceConfig(pciAddress, gpuSaveArea);
pciRestoreBridgeConfig(bridgePciAddress, bridgeSaveArea);
SetDeviceStatusVar(pciAddress, configUpdated ? StatusVar_GpuStrapsConfigured : StatusVar_GpuStrapsPreConfigured);
uint_least16_t capabilityOffset = pciFindExtCapability(pciAddress, PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID);
uint_least32_t barSizeMask = capabilityOffset ? pciRebarGetPossibleSizes(pciAddress, capabilityOffset, vendorId, deviceId, PCI_BAR_IDX1) : 0u;
if (barSizeMask)
{
if (barSizeMask & UINT32_C(1) << (barSizeSelector.barSizeSelector + 6u))
SetDeviceStatusVar(pciAddress, StatusVar_GpuStrapsConfirm);
else
SetDeviceStatusVar(pciAddress, StatusVar_GpuStrapsNoConfirm);
}
else
if (isTuringGPU(deviceId))
SetDeviceStatusVar(pciAddress, StatusVar_GpuNoReBarCapability);
if (nPciBarSizeSelector == TARGET_PCI_BAR_SIZE_GPU_ONLY)
{
if (capabilityOffset && (barSizeMask & UINT32_C(0x0000'0001) << (barSizeSelector.barSizeSelector + 6u) || sizeMaskOverride.sizeMaskOverride))
{
if ((barSizeMask & UINT32_C(0x0000'0001) << (barSizeSelector.barSizeSelector + 6u)) == 0)
SetDeviceStatusVar(pciAddress, StatusVar_GpuReBarSizeOverride);
if (pciRebarSetSize(pciAddress, capabilityOffset, PCI_BAR_IDX1, (uint_least8_t)(barSizeSelector.barSizeSelector + 6u)))
SetDeviceStatusVar(pciAddress, StatusVar_GpuReBarConfigured);
}
}
else
if (nPciBarSizeSelector == TARGET_PCI_BAR_SIZE_GPU_STRAPS_ONLY)
{
EFI_EVENT eventTimer = NULL;
if (EFI_ERROR((status = gBS->CreateEvent(EVT_TIMER, TPL_APPLICATION, NULL, NULL, &eventTimer))))
SetDeviceEFIError(pciAddress, EFIError_CreateTimer, status);
else
{
if (EFI_ERROR((status = gBS->SetTimer(eventTimer, TimerRelative, 1'000'000u))))
SetDeviceEFIError(pciAddress, EFIError_SetupTimer, status);
else
{
UINTN eventIndex = 0u;
if (EFI_ERROR((status = gBS->WaitForEvent(1, &eventTimer, &eventIndex))))
SetDeviceEFIError(pciAddress, EFIError_WaitTimer, status);
}
if (EFI_ERROR((status = gBS->CloseEvent(eventTimer))))
SetDeviceEFIError(pciAddress, EFIError_CloseTimer, status);
}
}
// gDS->FreeIoSpace(bridgeIoPortRangeBegin, SIZE_1KB / 2u);
// }
// else
// SetStatusVar(StatusVar_EFIAllocationError);
//
// gDS->FreeMemorySpace(baseAddress0, SIZE_32MB);
// }
// else
// SetStatusVar(StatusVar_EFIAllocationError);
}
bool NvStraps_CheckBARSizeListAdjust(UINTN pciAddress, uint_least16_t vid, uint_least16_t did, uint_least16_t subsysVenID, uint_least16_t subsysDevID, uint_least8_t barIndex)
{
if (vid == TARGET_GPU_VENDOR_ID && subsysVenID != WORD_BITMASK && subsysDevID != WORD_BITMASK && barIndex == PCI_BAR_IDX1)
{
uint_least8_t bus, device, func;
pciUnpackAddress(pciAddress, &bus, &device, &func);
NvStraps_BarSize barSizeSelector = NvStrapsConfig_LookupBarSize(config, did, subsysVenID, subsysDevID, bus, device, func);
if (barSizeSelector.priority == UNCONFIGURED || barSizeSelector.barSizeSelector == BarSizeSelector_None || barSizeSelector.barSizeSelector == BarSizeSelector_Excluded)
return false;
NvStraps_BarSizeMaskOverride sizeMaskOverride = NvStrapsConfig_LookupBarSizeMaskOverride(config, did, subsysVenID, subsysDevID, bus, device, func);
if (sizeMaskOverride.sizeMaskOverride)
{
NvStraps_BridgeConfig const *bridgeConfig = NvStrapsConfig_LookupBridgeConfig(config, bus);
return isBridgeEnumerated(pciPackLocation(bridgeConfig->bridgeBus, bridgeConfig->bridgeDevice, bridgeConfig->bridgeFunction));
}
return false;
}
return false;
}
uint_least32_t NvStraps_AdjustBARSizeList(UINTN pciAddress, uint_least16_t vid, uint_least16_t did, uint_least16_t subsysVenID, uint_least16_t subsysDevID, uint_least8_t barIndex, uint_least32_t barSizeMask)
{
uint_least8_t bus, device, func;
pciUnpackAddress(pciAddress, &bus, &device, &func);
NvStraps_BarSize barSizeSelector = NvStrapsConfig_LookupBarSize(config, did, subsysVenID, subsysDevID, bus, device, func);
if (barSizeSelector.priority == UNCONFIGURED || barSizeSelector.barSizeSelector == BarSizeSelector_None || barSizeSelector.barSizeSelector == BarSizeSelector_Excluded)
return barSizeMask;
if ((barSizeMask & UINT32_C(0x00000001) << (6u + (unsigned)barSizeSelector.barSizeSelector)) == 0u)
SetDeviceStatusVar(pciAddress, StatusVar_GpuReBarSizeOverride);
return barSizeMask | UINT32_C(0x00000001) << (6u + (unsigned)barSizeSelector.barSizeSelector);
}
// vim: ft=cpp