-
Notifications
You must be signed in to change notification settings - Fork 3
/
Copy pathSnakeGame.qsf
107 lines (105 loc) · 5.84 KB
/
SnakeGame.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
# Date created = 17:50:38 October 26, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# SnakeGame_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY SnakeGame
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:50:38 OCTOBER 26, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL Custom
set_global_assignment -name EDA_INPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_144 -to VGA_B
set_location_assignment PIN_1 -to VGA_G
set_location_assignment PIN_142 -to VGA_HS
set_location_assignment PIN_2 -to VGA_R
set_location_assignment PIN_143 -to VGA_VS
set_location_assignment PIN_23 -to clk
set_location_assignment PIN_68 -to color
set_location_assignment PIN_58 -to reset
set_location_assignment PIN_73 -to dir_out[0]
set_location_assignment PIN_76 -to dir_out[1]
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA
set_location_assignment PIN_30 -to res_x_one
set_location_assignment PIN_52 -to res_x_two
set_location_assignment PIN_39 -to res_y_one
set_location_assignment PIN_44 -to res_y_two
set_location_assignment PIN_128 -to sseg_an[0]
set_location_assignment PIN_129 -to sseg_an[1]
set_location_assignment PIN_132 -to sseg_an[2]
set_location_assignment PIN_133 -to sseg_an[3]
set_location_assignment PIN_127 -to sseg_a_to_dp[0]
set_location_assignment PIN_126 -to sseg_a_to_dp[1]
set_location_assignment PIN_125 -to sseg_a_to_dp[2]
set_location_assignment PIN_124 -to sseg_a_to_dp[3]
set_location_assignment PIN_121 -to sseg_a_to_dp[4]
set_location_assignment PIN_120 -to sseg_a_to_dp[5]
set_location_assignment PIN_119 -to sseg_a_to_dp[6]
set_location_assignment PIN_115 -to sseg_a_to_dp[7]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VERILOG_FILE src/modules/out/VGA/VGA_Draw.v
set_global_assignment -name VERILOG_FILE src/modules/out/VGA/VGA_Ctrl.v
set_global_assignment -name VERILOG_FILE src/modules/out/sseg/SSEG_Driver.v
set_global_assignment -name VERILOG_FILE src/modules/out/sseg/SSEG_Display.v
set_global_assignment -name VERILOG_FILE src/modules/shared/clks/game_upd_clk/game_upd_clk.v
set_global_assignment -name VERILOG_FILE src/modules/util/random/random_num_gen_63.v
set_global_assignment -name VERILOG_FILE src/modules/util/random/LFSR/LFSR.v
set_global_assignment -name VERILOG_FILE src/modules/input/joystick_input.v
set_global_assignment -name VERILOG_FILE src/modules/input/buttons.v
set_global_assignment -name VERILOG_INCLUDE_FILE src/definitions/initialization.vh
set_global_assignment -name VERILOG_FILE src/modules/util/rand_generator.v
set_global_assignment -name VERILOG_INCLUDE_FILE src/definitions/define.vh
set_global_assignment -name VERILOG_FILE src/modules/SnakeGame.v
set_global_assignment -name QIP_FILE src/modules/shared/clks/VGA_clk/VGA_clk.qip
set_global_assignment -name VERILOG_FILE src/modules/core_logic/game_logic.v
set_global_assignment -name VERILOG_INCLUDE_FILE src/definitions/sprites.vh