Change nRF5340DK board files to handle CPUNET pin configuration with DTS nodes

[crfosse]

Is your enhancement proposal related to a problem? Please describe.
Currently pins P1.0, P1.1, P0.10 and P0.11 are hard coded for UARTE use in nrf5340_cpunet_reset.c. The fact that these pins are unavailable when a nRF5340 application is configured to use both cores (for example when CONFIG_BT=y) is not communicated at all to the user. Any configuration of these pins in DTS or in the application will silently be ignored. For example, any GPIO interrupts tied to these pins won't work.

Describe the solution you'd like
This is already explained in nrf5340_cpunet_reset.c with the following comment: /* This should come from DTS, possibly an overlay. */. Board configuration with DTS has already been implemented for the nRF9160DK and a similar approach can likely be used for the nRF5340DK.

Describe alternatives you've considered
You can easily work around this by using different pins, but the fact that the mentioned pins are unavailable should be communicated to the user through documentation and build warnings.

Additional context
I've tested this myself on an nRF5340DK with the /samples/basic/button sample.

[anangl]

Addressed in #43047.