Clock control settings for MCUX Audio Clock are Incorrect

[NickolasLapp]

Describe the bug
The Audio PLL Clock Rate calculation for the I2S Clock is incorrect, resulting in incorrect downstream clocks (for example I2S MCLK). Additionally, the PLL configuration for NXP RT parts configures the PLL settings outside of their allowable ranges according to the datasheet.

This affects:

• MCUX Clock Control Driver when using the Audio PLL
• IMX RT Parts configuring the SAI module in DTS

To Reproduce
Steps to reproduce the behavior:
Run the sample I2S test code on a compatible NXP RT part:
https://github.com/zephyrproject-rtos/zephyr/tree/main/tests/drivers/i2s/i2s_api

1. west build -p auto -b mimxrt1060_evk tests/drivers/i2s/i2s_api
2. Probe the MCLK output line with a scope or logic analyzer and measure the MClk frequency
3. Compare it to the calculated MCLK rate (from the driver: here)
4. Notice the measured value and the calculated value do not agree.

Expected behavior
The calculated mclk rate should match the actual produced rate and the driver should set up the PLL according to datasheet specifications.

Impact
I2S cannot be correctly configured on RT parts.

[NickolasLapp]

Fixed by: #44935