Fix timer for Blargg interrupt test?

Baekalfen · Sep 15, 2024 · d13246a · d13246a
1 parent f7f6e03
commit d13246a
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Showing 2 changed files with 4 additions and 8 deletions.
diff --git a/pyboy/core/timer.pxd b/pyboy/core/timer.pxd
@@ -24,8 +24,6 @@ cdef class Timer:
     cdef void reset(self) noexcept nogil
     @cython.locals(divider=cython.int)
     cdef bint tick(self, uint64_t) noexcept nogil
-    @cython.locals(divider=cython.int, cyclesleft=cython.uint)
-    cdef int64_t cycles_to_interrupt(self) noexcept nogil
 
     cdef void save_state(self, IntIOInterface) noexcept
     cdef void load_state(self, IntIOInterface, int) noexcept
diff --git a/pyboy/core/timer.py b/pyboy/core/timer.py
@@ -41,6 +41,7 @@ def tick(self, _cycles):
         if cycles == 0:
             return False
         self.last_cycles = _cycles
+
         self.DIV_counter += cycles
         self.DIV += (self.DIV_counter >> 8) # Add overflown bits to DIV
         self.DIV_counter &= 0xFF # Remove the overflown bits
@@ -54,21 +55,18 @@ def tick(self, _cycles):
         divider = self.dividers[self.TAC & 0b11]
 
         ret = False
-        if self.TIMA_counter >= 1 << divider:
-            self.TIMA_counter -= 1 << divider # Keeps possible remainder
+        while self.TIMA_counter >= (1 << divider):
+            self.TIMA_counter -= (1 << divider) # Keeps possible remainder
             self.TIMA += 1
 
             if self.TIMA > 0xFF:
                 self.TIMA = self.TMA
                 self.TIMA &= 0xFF
                 ret = True
-                # return True
+        # self._cycles_to_interrupt = ((0x100 - self.TIMA) * (1 << divider)) - self.TIMA_counter
         self._cycles_to_interrupt = ((0x100 - self.TIMA) << divider) - self.TIMA_counter
         return ret
 
-    def cycles_to_interrupt(self):
-        return self._cycles_to_interrupt
-
     def save_state(self, f):
         f.write(self.DIV)
         f.write(self.TIMA)