AHB_APB_VERIFICATION

verfication code Responsibilities: 1)Architected the class based verification environment in UVM. 2)Defined Verification Plan. l 66% 3)Verified the RTL module with UVM Test Bench with different test scenarios like single READ,WRITE &Burst READ,WRITE with different burst lengths. 4)Generated functional and code coverage for the RTL verification sign-off.

Skills: EDA TOOL: questa HVL: System Verilog TB:UVM

Name		Name	Last commit message	Last commit date
Latest commit History 12 Commits
.github/workflows		.github/workflows
Makefile		Makefile
README.md		README.md
ahb_agt.sv		ahb_agt.sv
ahb_apb_top.v		ahb_apb_top.v
ahb_config.sv		ahb_config.sv
ahb_drv.sv		ahb_drv.sv
ahb_if.sv		ahb_if.sv
ahb_mon.sv		ahb_mon.sv
ahb_seq.sv		ahb_seq.sv
ahb_seqr.sv		ahb_seqr.sv
ahb_slave.v		ahb_slave.v
ahb_top.sv		ahb_top.sv
ahb_xtn.sv		ahb_xtn.sv
apb_agt.sv		apb_agt.sv
apb_config.sv		apb_config.sv
apb_controller.v		apb_controller.v
apb_drv.sv		apb_drv.sv
apb_if.sv		apb_if.sv
apb_interface.v		apb_interface.v
apb_mon.sv		apb_mon.sv
apb_seq.sv		apb_seq.sv
apb_seqr.sv		apb_seqr.sv
apb_top.sv		apb_top.sv
apb_xtn.sv		apb_xtn.sv
definitions.v		definitions.v
env_config.sv		env_config.sv
pkg.sv		pkg.sv
scoreboard.sv		scoreboard.sv
tb.sv		tb.sv
top.sv		top.sv
virtual_seqr.sv		virtual_seqr.sv
virtual_seqs.sv		virtual_seqs.sv
vtest.sv		vtest.sv

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