Gonadeepika / Counter_verification Public

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1)Architected the class based verification environment in UVM. 2)Defined Verification Plan. l 66% 3)Verified the RTL module with UVM Test Bench with different test scenarios like single READ,WRITE &Burst READ,WRITE with different burst lengths. 4)Generated functional and code coverage for the RTL verification sign-off. Skills

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
.coun_pkg.sv.swo		.coun_pkg.sv.swo
.coun_pkg.sv.swp		.coun_pkg.sv.swp
.count_if.sv.swp		.count_if.sv.swp
.count_trans.sv.swo		.count_trans.sv.swo
.count_trans.sv.swp		.count_trans.sv.swp
.counter_env.sv.swo		.counter_env.sv.swo
.counter_env.sv.swp		.counter_env.sv.swp
.gen.sv.swo		.gen.sv.swo
.gen.sv.swp		.gen.sv.swp
.mode64		.mode64
.rd_mon.sv.swo		.rd_mon.sv.swo
.rd_mon.sv.swp		.rd_mon.sv.swp
.rf_mod.sv.swo		.rf_mod.sv.swo
.rf_mod.sv.swp		.rf_mod.sv.swp
.rtl.sv.swp		.rtl.sv.swp
.sb.sv.swp		.sb.sv.swp
.test.sv.swp		.test.sv.swp
.top.sv.swo		.top.sv.swo
.top.sv.swp		.top.sv.swp
.wr_drv.sv.swn		.wr_drv.sv.swn
.wr_drv.sv.swo		.wr_drv.sv.swo
.wr_drv.sv.swp		.wr_drv.sv.swp
.wr_mon.sv.swo		.wr_mon.sv.swo
.wr_mon.sv.swp		.wr_mon.sv.swp
Makefile		Makefile
README.md		README.md
comp.log		comp.log
coun_pkg.sv		coun_pkg.sv
count_if.sv		count_if.sv
count_trans.sv		count_trans.sv
counter_env.sv		counter_env.sv
gen.sv		gen.sv
rd_mon.sv		rd_mon.sv
rf_mod.sv		rf_mod.sv
rtl.sv		rtl.sv
sb.sv		sb.sv
simv		simv
test.sv		test.sv
top.sv		top.sv
ucli.key		ucli.key
vcs.log		vcs.log
verdi_config_file		verdi_config_file
wr_drv.sv		wr_drv.sv
wr_mon.sv		wr_mon.sv