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meta: add CI configuration

Closes atsams-rs#21

See merge request embedded-rust/atsamx7x-hal!14
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tmplt committed Jul 11, 2022
2 parents 4a6b237 + e49eae0 commit 466f36f
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10 changes: 10 additions & 0 deletions .ci/Dockerfile
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@@ -0,0 +1,10 @@
FROM rust:1.61.0-slim

RUN apt-get update && apt-get install -y \
binutils-arm-none-eabi \
git \
&& rm -rf /var/lib/apt/lists/*

RUN rustup target add thumbv7em-none-eabihf && \
rustup component add rustfmt && \
rustup component add clippy
1 change: 1 addition & 0 deletions .ci/README.md
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@@ -0,0 +1 @@
This directory contains the `Dockerfile` used in the CI of the HAL. See [GitLab Container Registry documentation](https://git.grepit.se/embedded-rust/atsamx7x-hal/container_registry) for update instructions.
57 changes: 57 additions & 0 deletions .gitlab-ci.yml
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@@ -0,0 +1,57 @@
image: "registry.git.grepit.se/embedded-rust/atsamx7x-hal"

stages:
- HAL
- examples
- lint

default:
before_script:
- rustup show

samv71q21b:
stage: HAL
script:
- cd hal
- cargo check --features samv71q21b,unproven

same70n21b:
stage: HAL
script:
- cd hal
- cargo check --features same70n21b,unproven

e70:
stage: examples
script:
- cd boards/atsame70_xpro
- cargo check --examples

v71:
stage: examples
script:
- cd boards/atsamv71_xult
- cargo check --examples

fmt:
stage: lint
needs: []
script:
- cd hal
- cargo fmt -- --check
- cd ../boards/atsame70_xpro
- cargo fmt -- --check
- cd ../atsamv71_xult
- cargo fmt -- --check

clippy:
stage: lint
allow_failure: true
needs: ["samv71q21b"]
script:
- cd hal
- cargo clippy --no-deps --features samv71q21b,unproven
- cd ../boards/atsame70_xpro
- cargo clippy --examples --no-deps
- cd ../atsamv71_xult
- cargo clippy --examples --no-deps
2 changes: 1 addition & 1 deletion hal/build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ fn main() -> Result<(), &'static str> {
fn feat(f: &str) -> bool {
env::var(format!(
"CARGO_FEATURE_{}",
f.to_ascii_uppercase().replace("-", "_")
f.to_ascii_uppercase().replace('-', "_")
))
.is_ok()
}
Expand Down
4 changes: 2 additions & 2 deletions hal/src/efc.rs
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ use crate::target_device::EFC;
/// The voltage which drives the MCU.
///
/// Refer to §58 and §59.
#[derive(PartialEq)]
#[derive(Eq, PartialEq)]
pub enum VddioLevel {
/// VDDIO = 3.3V, typical
V3,
Expand Down Expand Up @@ -49,7 +49,7 @@ impl Efc {
/// The number of flash wait states for a read operation.
///
/// Note: The number of cycles a read takes is 1 + FWS.
#[derive(Debug, PartialEq, Copy, Clone)]
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
#[repr(u8)]
enum FlashWaitStates {
Zero,
Expand Down
53 changes: 36 additions & 17 deletions hal/src/pio/bank.rs
Original file line number Diff line number Diff line change
Expand Up @@ -97,18 +97,18 @@ impl<B: PinBank> Iterator for BankInterruptsIter<B> {
match self.idx {
32.. => {
// We have iterated over all pins: nothing more to do.
return None;
None
}
idx if self.irq & (1 << idx) != 0 => {
// Pin number `idx` had a pending interrupt.
let pin = self.idx;
self.idx = self.idx + 1;
self.idx += 1;
Some(pin)
}
_ => {
// Pin number `idx` did not have a pending interrupt:
// advance to the next pin.
self.idx = self.idx + 1;
self.idx += 1;
self.next()
}
}
Expand Down Expand Up @@ -253,28 +253,41 @@ macro_rules! bank {
macro_rules! banks {
(
$(
$( #[$cfg1:meta] )?
$Bank:ident {
$(
$( #[$cfg:meta] )?
$( #[$cfg2:meta] )?
($Id:ident, $NUM:literal),
)+
}
)+
) => {
$(
$(
$( #[$cfg] )?
pin_id!($Bank, $Id, $NUM);
)+
bank!(
$Bank,
$(
$( #[$cfg] )?
$Id,
)+
);
impl PinBank for $Bank {
const DYN: DynBank = DynBank::$Bank;
paste! {
$( #[$cfg1] )?
mod [<$Bank:lower _impl>] {
use super::*;

$(
$( #[$cfg2] )?
pin_id!($Bank, $Id, $NUM);
)+

bank!(
$Bank,
$(
$( #[$cfg2] )?
$Id,
)+
);

impl PinBank for $Bank {
const DYN: DynBank = DynBank::$Bank;
}

}
$( #[$cfg1] )?
pub use [<$Bank:lower _impl>]::*;
}
)+
};
Expand All @@ -288,6 +301,7 @@ banks!(
(PA3, 3),
(PA4, 4),
(PA5, 5),
#[cfg(feature = "pins-144")]
(PA6, 6),
(PA7, 7),
(PA8, 8),
Expand All @@ -311,6 +325,7 @@ banks!(
(PA26, 26),
(PA27, 27),
(PA28, 28),
#[cfg(feature = "pins-144")]
(PA29, 29),
(PA30, 30),
(PA31, 31),
Expand All @@ -331,6 +346,7 @@ banks!(
(PB13, 13),
}

#[cfg(feature = "pins-144")]
C {
(PC0, 0),
(PC1, 1),
Expand Down Expand Up @@ -390,17 +406,20 @@ banks!(
(PD20, 20),
(PD21, 21),
(PD22, 22),
#[cfg(feature = "pins-144")]
(PD23, 23),
(PD24, 24),
(PD25, 25),
(PD26, 26),
(PD27, 27),
(PD28, 28),
#[cfg(feature = "pins-144")]
(PD29, 29),
(PD30, 30),
(PD31, 31),
}

#[cfg(feature = "pins-144")]
E {
(PE0, 0),
(PE1, 1),
Expand Down
8 changes: 6 additions & 2 deletions hal/src/pio/dynpin.rs
Original file line number Diff line number Diff line change
Expand Up @@ -82,12 +82,14 @@ pub enum DynPinMode {

/// Value-level `enum` regresenting [`Pin`] banks
#[doc(hidden)]
#[derive(PartialEq, Clone, Copy)]
#[derive(Eq, PartialEq, Clone, Copy)]
pub enum DynBank {
A,
B,
#[cfg(feature = "pins-144")]
C,
D,
#[cfg(feature = "pins-144")]
E,
}

Expand All @@ -96,16 +98,18 @@ impl DynBank {
match self {
Self::A => PIOA::ptr(),
Self::B => PIOB::ptr(),
#[cfg(feature = "pins-144")]
Self::C => PIOC::ptr(),
Self::D => PIOD::ptr(),
#[cfg(feature = "pins-144")]
Self::E => PIOE::ptr(),
}
}
}

/// Value-level `struct` representing [`Pin`] IDs
#[doc(hidden)]
#[derive(PartialEq, Clone, Copy)]
#[derive(Eq, PartialEq, Clone, Copy)]
pub struct DynPinId {
pub bank: DynBank,
pub num: u8,
Expand Down
5 changes: 3 additions & 2 deletions hal/src/pio/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -102,12 +102,13 @@ use crate::target_device::{
// All PIO banks below use the same register block definition.
pioa::RegisterBlock,

// Banks common to all chip sizes.
PIOA,
PIOB,
PIOC,
PIOD,
PIOE,
};
#[cfg(feature = "pins-144")]
use crate::target_device::{PIOC, PIOE};

pub mod pin;
pub use pin::*;
Expand Down
6 changes: 5 additions & 1 deletion hal/src/pio/pin.rs
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ pub(in crate::pio) struct Registers<I: PinId> {
id: PhantomData<I>,
}

unsafe impl<I: PinId> RegisterInterface for Registers<I> {
impl<I: PinId> RegisterInterface for Registers<I> {
#[inline]
fn id(&self) -> DynPinId {
I::DYN
Expand Down Expand Up @@ -226,21 +226,25 @@ where
}

#[inline]
#[allow(clippy::bool_comparison)]
pub(in crate::pio) fn _is_written_high(&self) -> bool {
self.regs.read_out_pin() == true
}

#[inline]
#[allow(clippy::bool_comparison)]
pub(in crate::pio) fn _is_written_low(&self) -> bool {
self.regs.read_out_pin() == false
}

#[inline]
#[allow(clippy::bool_comparison)]
pub(in crate::pio) fn _is_read_high(&self) -> bool {
self.regs.read_in_pin() == true
}

#[inline]
#[allow(clippy::bool_comparison)]
pub(in crate::pio) fn _is_read_low(&self) -> bool {
self.regs.read_in_pin() == false
}
Expand Down
14 changes: 7 additions & 7 deletions hal/src/pio/reg.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ use crate::target_device::pioa::RegisterBlock;

use super::dynpin::*;

pub(in crate::pio) unsafe trait RegisterInterface {
pub(in crate::pio) trait RegisterInterface {
fn id(&self) -> DynPinId;

/// Return the `u32` mask to set/clear a bit for this
Expand All @@ -21,14 +21,14 @@ pub(in crate::pio) unsafe trait RegisterInterface {
fn change_mode(&mut self, mode: DynPinMode) {
match mode {
DynPinMode::Reset => unimplemented!(),
DynPinMode::Peripheral(a) => self.into_peripheral(a),
DynPinMode::Output => self.into_output(),
DynPinMode::Input => self.into_input(),
DynPinMode::Peripheral(a) => self.as_peripheral(a),
DynPinMode::Output => self.as_output(),
DynPinMode::Input => self.as_input(),
}
}

#[inline]
fn into_peripheral(&mut self, cfg: DynPeripheral) {
fn as_peripheral(&mut self, cfg: DynPeripheral) {
use DynPeripheral::*;
let (sr0, sr1) = match cfg {
A => (false, false),
Expand Down Expand Up @@ -58,7 +58,7 @@ pub(in crate::pio) unsafe trait RegisterInterface {
}

#[inline]
fn into_output(&mut self) {
fn as_output(&mut self) {
// set initial output state as low (0)
self.write_pin(false);

Expand All @@ -75,7 +75,7 @@ pub(in crate::pio) unsafe trait RegisterInterface {
}

#[inline]
fn into_input(&mut self) {
fn as_input(&mut self) {
// take pin from peripheral
self.reg().pio_per.write(|w| unsafe { w.bits(self.mask()) });

Expand Down
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