Multi-cycle processor RISC-V with RV32I/E[M] implementation, developed during some days off.
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The official language adopted by the project is Brazilian Portuguese; therefore, most of the documentation and commits are in this language.
The processor was implemented using Verilog HDL and features a multi-cycle implementation without pipelining.
The software directory contains examples and tests written in Assembly, along with their respective memory files. Additionally, there's a script available to convert Assembly code into memory files. The official processor firmware is also available in the software/firmware directory.
The tests directory includes various tests built using Iverilog. All tests in this directory are compatible with Iverilog.
- Baby RISCO 5 - RV32E optimized to TinyTapeout: https://github.com/JN513/Baby-Risco-5
- Pequeno RISCO 5 - RV32I single cycle implementation (ARCHIVED): https://github.com/JN513/Pequeno-Risco-5/
- RISCO 5 - RV32I/E[M]: https://github.com/JN513/Risco-5
- Grande RISCO 5 - RV32I Implementation with pipeline: https://github.com/JN513/Grande-Risco-5
- RISCO 5 Bodybuilder - RV64I: Still in speculative phase
- RISCO 5S - RV32IM Simulator writing in C language: https://github.com/JN513/Risco-5S
The official documentation is available at: https://jn513.github.io/Risco-5/. If you have any questions or suggestions, feel free to use the ISSUES section on GitHub. Contributions are welcome, and all Pull requests will be reviewed and merged if possible.
If you'd like to contribute to the project, please feel free to do so. The CONTRIBUTING.md file contains the necessary instructions.
This project is licensed under the CERN-OHL-P-2.0 license, which grants full freedom for use. The software is licensed under the MIT License, and the documentation under CC BY-SA 4.0.
Logo author: Mateus Luck
