update tb

06_cpu_register/cpu_register.sv

@@ -10,7 +10,7 @@ module cpu_register(
 );
     logic [31:0] DATA [31:0];
     // 初期値
-    always @(*) begin
+    always @(posedge clk) begin
         DATA[0] = 49;
         DATA[1] = 7;
         DATA[2] = 3;

08_mycpu/cpu.sv

@@ -1,5 +1,4 @@
 // reg+ALUのみCPU
-
 module cpuv1(
     input logic clk,
     input logic [31:0] inst
@@ -15,7 +14,7 @@ module cpuv1(
     cpu_register r1(
         .addr1(addr1),
         .addr2(addr2),
-        .addrw(addr2),
+        .addrw(addrw),
         .writeen(writeen),
         .writeint(out),
         .RD1(a),

08_mycpu/cpu_tb.sv

@@ -0,0 +1,15 @@
+module cpu_tb;
+    reg [31:0] inst;
+    reg clk;
+
+    // 加算命令
+    initial begin
+        inst = 32'b00000000000010000010000000000000;
+        clk = 0;
+    end
+    // CPU
+    cpuv1 c1(.*);
+
+    always #2
+        clk = clk + 1;
+endmodule