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fix bugs
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kentaroy47 committed Nov 26, 2021
1 parent b634a6d commit 87f5267
Showing 1 changed file with 3 additions and 7 deletions.
10 changes: 3 additions & 7 deletions 98_debug/cputest.sv
Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,7 @@ module regista(input logic[4:0]addrw,
DATA[addrw] <= (writeen) ? writeint:0;
endmodule


module cpu(input logic clk,
input logic[31:0]inst);

Expand All @@ -86,10 +87,5 @@ module cpu(input logic clk,
regista u7(.addr1(inst[12:8]),.addr2(inst[17:13]),.addrw(inst[22:18])
,.writeint(y),.clk(clk),.RD1(a),.RD2(b),.writeen(writeen));

endmodule






endmodule

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