change dir names

Keio-CSG · Nov 18, 2021 · ab53900 · ab53900
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commit ab53900
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diff --git a/helloworld/hello.v → 00_helloworld_verilog/hello.v b/helloworld/hello.v → 00_helloworld_verilog/hello.v
diff --git a/addertest/adder4.v → 01_addertest_verilog/adder4.v b/addertest/adder4.v → 01_addertest_verilog/adder4.v
diff --git a/addertest/adder_test.v → 01_addertest_verilog/adder_test.v b/addertest/adder_test.v → 01_addertest_verilog/adder_test.v
diff --git a/chap4-logic-systemverilog/chap4_logic.sv → 02_chap4_logic_systemverilog/chap4_logic.sv b/chap4-logic-systemverilog/chap4_logic.sv → 02_chap4_logic_systemverilog/chap4_logic.sv
diff --git a/chap4-logic-systemverilog/chap4_test.sv → 02_chap4_logic_systemverilog/chap4_test.sv b/chap4-logic-systemverilog/chap4_test.sv → 02_chap4_logic_systemverilog/chap4_test.sv
diff --git a/cpu-example/MEMORY.v → 99_cpuexample_verilog/MEMORY.v b/cpu-example/MEMORY.v → 99_cpuexample_verilog/MEMORY.v
diff --git a/cpu-example/cpu_modules.v → 99_cpuexample_verilog/cpu_modules.v b/cpu-example/cpu_modules.v → 99_cpuexample_verilog/cpu_modules.v
diff --git a/cpu-example/testbench_mips.v → 99_cpuexample_verilog/testbench_mips.v b/cpu-example/testbench_mips.v → 99_cpuexample_verilog/testbench_mips.v