Simplify SBI implementation using derive macro RustSBI

Cargo.toml

@@ -20,5 +20,10 @@ page_table_entry = { path = "../page_table_entry" }
 [target.'cfg(target_arch = "riscv64")'.dependencies]
 riscv = { git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] }
 riscv-decode = { git = "https://github.com/KuangjuX/riscv-decode.git" }
-sbi-spec = { version = "0.0.6", features = ["legacy"] }
-sbi-rt = {version = "0.0.2", features = ["integer-impls", "legacy"]}
+sbi-spec = "0.0.7-alpha.3"
+rustsbi = { git = "https://github.com/rustsbi/rustsbi", features = ["forward"] }
+
+[lib]
+name = "hypercraft"
+test = false
+bench = false

src/arch/riscv/mem_extable.S

@@ -26,7 +26,8 @@ _copy_to_guest:
     beq   t2, a2, _ret_from_copy
     lb    t3, (a1)
 2:
-    hsv.b t3, (a0)
+    /* hsv.b t3, (a0) */
+    .insn r 0x73, 0x4, 0x31, x0, t3, a0
     add_extable 2b
     addi  a0, a0, 1
     addi  a1, a1, 1
@@ -44,7 +45,8 @@ _copy_from_guest:
 1:
     beq   t2, a2, _ret_from_copy
 2:
-    hlv.b t3, (a1)
+    /* hlv.b t3, (a1) */
+    .insn i 0x73, 0x4, t3, a1, 0x600
     add_extable 2b
     sb    t3, (a0)
     addi  a0, a0, 1
@@ -66,7 +68,8 @@ _fetch_guest_instruction:
     // a fault and will stick SCAUSE in t1.
     la    t0, 4f
 1:
-    hlvx.hu t2, (a0)
+    /* hlvx.hu t2, (a0) */
+    .insn i 0x73, 0x4, t2, a0, 0x643
     add_extable 1b
     sh    t2, (a1)
     addi  a0, a0, 2
@@ -77,7 +80,8 @@ _fetch_guest_instruction:
     bne   t2, t3, 3f
     // Load the next half-word.
 2:
-    hlvx.hu t2, (a0)
+    /* hlvx.hu t2, (a0) */
+    .insn i 0x73, 0x4, t2, a0, 0x643
     add_extable 2b
     sh    t2, (a1)
 3:

src/arch/riscv/mod.rs

@@ -22,7 +22,6 @@ pub use vmexit::VmExitInfo;
 use self::csrs::{traps, ReadWriteCsr, RiscvCsrTrait, CSR};
 use self::devices::plic::PlicState;
 use self::vcpu::VmCpuRegisters;
-use sbi::BaseFunction;
 
 /// Initialize the hypervisor runtime.
 pub fn init_hv_runtime() {

src/arch/riscv/sbi.rs

@@ -0,0 +1,25 @@
+use crate::{HyperError, HyperResult};
+
+/// SBI Message used to invoke the specfified SBI extension in the firmware.
+#[derive(Clone, Copy, Debug)]
+pub struct SbiMessage {
+    /// SBI extension ID.
+    pub extension: usize,
+    /// SBI function ID, if applicable.
+    pub function: usize,
+    /// SBI parameters.
+    pub params: [usize; 6],
+}
+
+impl SbiMessage {
+    /// Creates an SbiMessage struct from the given GPRs. Intended for use from the ECALL handler
+    /// and passed the saved register state from the calling OS. A7 must contain a valid SBI
+    /// extension and the other A* registers will be interpreted based on the extension A7 selects.
+    pub fn from_regs(args: &[usize]) -> Self {
+        SbiMessage {
+            extension: args[7],
+            function: args[6],
+            params: [args[0], args[1], args[2], args[3], args[4], args[5]],
+        }
+    }
+}

src/arch/riscv/vcpu.rs

@@ -308,7 +308,7 @@ impl<H: HyperCraftHal> VCpu<H> {
         use scause::{Exception, Interrupt, Trap};
         match scause.cause() {
             Trap::Exception(Exception::VirtualSupervisorEnvCall) => {
-                let sbi_msg = SbiMessage::from_regs(regs.guest_regs.gprs.a_regs()).ok();
+                let sbi_msg = SbiMessage::from_regs(regs.guest_regs.gprs.a_regs());
                 VmExitInfo::Ecall(sbi_msg)
             }
             Trap::Interrupt(Interrupt::SupervisorTimer) => VmExitInfo::TimerInterruptEmulation,