A C-based cache simulator that tracks memory hits, misses, and evictions to model cache performance.
This project is a C-based cache simulator designed to analyze memory access patterns by simulating cache behavior for various configurations, such as direct-mapped and set-associative caches. It tracks hits, misses, and evictions based on cache replacement policies, including Least Recently Used (LRU). The simulator processes memory traces to provide insights into cache efficiency, helping users understand the impact of caching strategies on system performance.