drivers: versal: add support for new TRNG IP

Versal Net TRNG is very close to Versal but includes hardware DF. This patch adds support for this. Signed-off-by: Jeremie Corbier <[email protected]>
OP-TEE · Feb 3, 2025 · 9835f1f · 9835f1f
1 parent 049b232
commit 9835f1f
Show file tree

Hide file tree

Showing 4 changed files with 42 additions and 1 deletion.
diff --git a/core/arch/arm/plat-versal/conf.mk b/core/arch/arm/plat-versal/conf.mk
@@ -76,6 +76,7 @@ CFG_VERSAL_PM ?= y
 
 # TRNG driver
 $(call force, CFG_VERSAL_RNG_DRV,y)
+$(call force, CFG_VERSAL_RNG_DRV_V2,y)
 $(call force, CFG_WITH_SOFTWARE_PRNG,n)
 
 ifeq ($(PLATFORM_FLAVOR),net)

diff --git a/core/drivers/crypto/versal/pki/ecc_pki_engine.c b/core/drivers/crypto/versal/pki/ecc_pki_engine.c
@@ -29,6 +29,7 @@
 static struct versal_trng ecc_pki_trng = {
 	.cfg.base = TRNG_BASE,
 	.cfg.len = TRNG_SIZE,
+	.cfg.version = TRNG_V2,
 };
 
 static TEE_Result versal_ecc_trng_init(void)

diff --git a/core/drivers/versal_trng.c b/core/drivers/versal_trng.c
@@ -75,12 +75,34 @@
 #define TRNG_STATUS_DTF_MASK		BIT(1)
 #define TRNG_STATUS_DONE_MASK		BIT(0)
 #define TRNG_CTRL			0x08
+#define TRNG_CTRL_PERSODISABLE		BIT(10)
+#define TRNG_CTRL_SINGLEGENMODE		BIT(9)
 #define TRNG_CTRL_EUMODE_MASK		BIT(8)
 #define TRNG_CTRL_PRNGMODE_MASK		BIT(7)
+#define TRNG_CTRL_TSTMODE_MASK		BIT(6)
 #define TRNG_CTRL_PRNGSTART_MASK	BIT(5)
 #define TRNG_CTRL_PRNGXS_MASK		BIT(3)
 #define TRNG_CTRL_TRSSEN_MASK		BIT(2)
 #define TRNG_CTRL_PRNGSRST_MASK		BIT(0)
+
+#if defined(CFG_VERSAL_RNG_DRV_V2)
+#define TRNG_CTRL_2			0x0C
+#define TRNG_CTRL_2_RCTCUTOFF_SHIFT	8
+#define TRNG_CTRL_2_RCTCUTOFF_MASK	GENMASK_32(16, 8)
+#define TRNG_CTRL_2_RCTCUTOFF_DEFVAL	0x21
+#define TRNG_CTRL_2_DIT_SHIFT		0
+#define TRNG_CTRL_2_DIT_MASK		GENMASK_32(4, 0)
+#define TRNG_CTRL_2_DIT_DEFVAL		0xC
+#define TRNG_CTRL_3			0x10
+#define TRNG_CTRL_3_APTCUTOFF_SHIFT	8
+#define TRNG_CTRL_3_APTCUTOFF_MASK	GENMASK_32(17, 8)
+#define TRNG_CTRL_3_APTCUTOFF_DEFVAL	0x264
+#define TRNG_CTRL_3_DLEN_SHIFT		0
+#define TRNG_CTRL_3_DLEN_MASK		GENMASK_32(7, 0)
+#define TRNG_CTRL_3_DLEN_DEFVAL		0x9
+#define TRNG_CTRL_4			0x14
+#endif
+
 #define TRNG_EXT_SEED_0			0x40
 /*
  * Below registers are not directly referenced in driver but are accessed
@@ -582,6 +604,12 @@ static TEE_Result trng_reseed_internal_nodf(struct versal_trng *trng,
 	uint8_t entropy[TRNG_SEED_LEN] = { 0 };
 	uint8_t *seed = NULL;
 
+#if defined(CFG_VERSAL_RNG_DRV_V2)
+	if (trng->cfg.version == TRNG_V2)
+		trng_clrset32(trng->cfg.addr, TRNG_CTRL_3,
+			      TRNG_CTRL_3_DLEN_MASK, TRNG_CTRL_3_DLEN_DEFVAL);
+#endif
+
 	switch (trng->usr_cfg.mode) {
 	case TRNG_HRNG:
 		trng_write32(trng->cfg.addr, TRNG_OSC_EN, TRNG_OSC_EN_VAL_MASK);
@@ -658,7 +686,7 @@ static TEE_Result trng_reseed_internal(struct versal_trng *trng,
 	else
 		trng->len = (mul + 1) * BYTES_PER_BLOCK;
 
-	if (trng->usr_cfg.df_disable) {
+	if (trng->usr_cfg.df_disable || trng->cfg.version == TRNG_V2) {
 		if (trng_reseed_internal_nodf(trng, eseed, str))
 			goto error;
 	} else {
@@ -963,6 +991,10 @@ static TEE_Result trng_kat_test(struct versal_trng *trng)
 	if (!trng)
 		return TEE_ERROR_GENERIC;
 
+	/* Self-tests are performed in HW */
+	if (trng->cfg.version == TRNG_V2)
+		return TEE_SUCCESS;
+
 	memcpy(&tests.init_seed, ext_seed, sizeof(ext_seed));
 	memcpy(tests.pstr, pers_str, sizeof(pers_str));
 
@@ -1051,6 +1083,7 @@ TEE_Result versal_trng_hw_init(struct versal_trng *trng,
 static struct versal_trng versal_trng = {
 	.cfg.base = TRNG_BASE,
 	.cfg.len = TRNG_SIZE,
+	.cfg.version = TRNG_V1,
 };
 
 TEE_Result hw_get_random_bytes(void *buf, size_t len)

diff --git a/core/include/drivers/versal_trng.h b/core/include/drivers/versal_trng.h
@@ -30,6 +30,11 @@
 #define BLK_SIZE		16
 #define MAX_ROUNDS		14
 
+enum trng_version {
+	TRNG_V1 = 1,
+	TRNG_V2 = 2,
+};
+
 enum trng_status {
 	TRNG_UNINITIALIZED = 0,
 	TRNG_HEALTHY,
@@ -47,6 +52,7 @@ struct trng_cfg {
 	paddr_t base;
 	vaddr_t addr;
 	size_t len;
+	enum trng_version version;
 };
 
 struct trng_usr_cfg {