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Update validation-scheme.md
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TimRudy authored Aug 28, 2020
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Expand Up @@ -40,8 +40,6 @@ As to what is happening for a typical pair of files, let's take a look.
Compare the 7485.v file (left) to the Verilog code inside 7485_Comparator.ice (right):

<img src="/images/7485_compare.png" title="Compare Verilog content" width="100%">
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Here's the context of these two pieces of code, for a quick recap:

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