More initial

TimRudy · Mar 21, 2020 · a7657e5 · a7657e5
1 parent a87e730
commit a7657e5
Show file tree

Hide file tree

Showing 5 changed files with 8 additions and 7 deletions.
diff --git a/source-7400/74147-tb.v b/source-7400/74147-tb.v
@@ -104,7 +104,7 @@ begin
   // 1. floating inputs behind any leading zero do not affect the output
 
   // 2. inputs that may affect the output must be tied to high or low logic voltage level
-  //    (e.g. pull-up resistor), so floating input at leading bit position is not tested
+  //    (e.g. pull-up resistor); therefore floating input at leading bit position is not tested
   //    and should not be simulated
 
   // bit 9 zero -> output is 9

diff --git a/source-7400/74148-tb.v b/source-7400/74148-tb.v
@@ -228,7 +228,7 @@ begin
   // 1. floating inputs behind any leading zero do not affect the output
 
   // 2. inputs that may affect the output must be tied to high or low logic voltage level
-  //    (e.g. pull-up resistor), so floating input at leading bit position is not tested
+  //    (e.g. pull-up resistor); therefore floating input at leading bit position is not tested
   //    and should not be simulated
 
   EI_bar = 1'b0;

diff --git a/source-7400/74155.v b/source-7400/74155.v
@@ -1,7 +1,7 @@
 // Dual 2-line to 4-line decoder/demultiplexer (inverted outputs)
 
-module ttl_74155 #(parameter BLOCKS_DIFFERENT = 2, BLOCK0 = 0, BLOCK1 = 1,
-                   WIDTH_OUT = 4, WIDTH_IN = $clog2(WIDTH_OUT), DELAY_RISE = 0, DELAY_FALL = 0)
+module ttl_74155 #(parameter BLOCKS_DIFFERENT = 2, BLOCK0 = 0, BLOCK1 = 1, WIDTH_OUT = 4,
+                   WIDTH_IN = $clog2(WIDTH_OUT), DELAY_RISE = 0, DELAY_FALL = 0)
 (
   input Enable1C,
   input Enable1G_bar,

diff --git a/source-7400/74283-tb.v b/source-7400/74283-tb.v
@@ -257,7 +257,8 @@ begin
   tbassert(C_out == 1'b1, "Test 14");
 #0
 
-  // change between input bits that are set to ones with null effect on outputs
+  // the following set of tests show transitions between input bits that are set to ones
+  // with null effect on outputs
 
   // 3 + 5 + Carry 0 -> 8
   A = 5'b00011;

diff --git a/source-7400/7485-tb.v b/source-7400/7485-tb.v
@@ -63,7 +63,7 @@ begin
       end
     endcase
 
-    // the following set of tests is affected by the cascading inputs:
+    // the following set of tests show the result is affected by the cascading inputs:
     // since A and B are equal, the output result is equality only if input Equal_in
     // is set; otherwise the output result tracks input ALess_in or input AGreater_in
 
@@ -186,7 +186,7 @@ begin
     tbassert2R(AGreater_out == AGreater_in, "Test", "12", i);
 #0
 
-    // the following set of tests is unaffected by the cascading inputs
+    // the following set of tests show the result is unaffected by the cascading inputs
     // (except for some set-ups of equality in the main inputs A and B)
 
     // single low bit set -> greater than