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8 changes: 4 additions & 4 deletions LICENSE
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GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007

Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.

Expand Down Expand Up @@ -645,7 +645,7 @@ the "copyright" line and a pointer to where the full notice is found.
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
along with this program. If not, see <https://www.gnu.org/licenses/>.

Also add information on how to contact you by electronic and paper mail.

Expand All @@ -664,11 +664,11 @@ might be different; for a GUI interface, you would use an "about box".
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<http://www.gnu.org/licenses/>.
<https://www.gnu.org/licenses/>.

The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<http://www.gnu.org/philosophy/why-not-lgpl.html>.
<https://www.gnu.org/licenses/why-not-lgpl.html>.
51 changes: 34 additions & 17 deletions README.md
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Expand Up @@ -22,23 +22,21 @@ The easiest way to use these devices is [download the collection](/releases/late

In Icestudio, go to `Tools > Collections > Add` and select the downloaded .zip file. Place and wire up your components, run and test the result. There's a variety of ways to provide inputs and view outputs; but no need for actual parts, wires or power supply.

Alternatively, you can download an individual device (.v file) and use it in your own simulation in Verilog. This is the way to go if you wish to set the parameters for #bits, #inputs per gate, #blocks in a device. See the Index to browse devices.
Alternatively, you can download an individual device ([74xx.v file](source-7400/74153.v)) and use it in your own simulation in Verilog. This is the way to go if you wish to set the parameters for #bits, #inputs per gate, #blocks in a device. See the Index to browse devices.

## Index

&ensp;&ensp;[Devices by type and name](device-index.md)

#### What are the 7400-series TTL chips?

&ensp;&ensp;They are digital logic: Gates, multiplexers, counters, registers, adders, multipliers and more

&ensp;&ensp;[7400-series integrated circuits (Wikipedia)][link-wiki-7400]
> ##### What are the 7400-series TTL chips?
>
> They are digital logic: Gates, multiplexers, counters, registers, adders, multipliers and more. See [Wikipedia full list][link-wiki-7400].
## Icestudio Design Flow

Welcome to virtual breadboarding.

Icestudio provides circuit simulation (for digital circuits) that's arbitrarily scalable. Explore, build and create, but most importantly, get near-instant feedback in testing your real hardware design. Each time you add a new input or a gate, hit "Build" and "Upload". In the parlance of a silicon fab, you've gone through a "spin". But you're actually programming a reusable and fairly inexpensive FPGA.
Icestudio provides circuit simulation (for digital circuits) that's arbitrarily scalable. Explore, build and create, but most importantly, get near-instant feedback in testing your real hardware design. Each time you add a new input or a gate, or an LED, hit "Build" and "Upload". In the parlance of a silicon fab, you've gone through a "spin". But you're actually programming a reusable and fairly inexpensive FPGA.

CAD-style layout using drag & drop
-> Full Verilog model
Expand All @@ -57,26 +55,40 @@ It's done with entirely open source tools (the IceStorm toolchain); and most of

## Tests and Validation

A test bench accompanies every device (74xx-tb.v file with 74xx.v file) and the tests are run automatically. Click on the "tests" badge below the main title at top of page to see the results of the validation run.
A test bench accompanies every device (74xx-tb.v file with 74xx.v file) and the tests are run automatically. You can click on the "tests" badge below the main title at top of page to see the logged results.

Tests are a definitive feature of the library. Test coverage will continue at the highest standard as the library expands going forward.

You have to "trust but verify" when scaling up a hardware design from lower-layer components.

<details>
<summary>Test benches</summary>
<br />

Tests are a definitive feature of the library. They must be:
IceChips tests must be:

1. Comprehensive
2. Meaningful (each test adding value)
3. Annotated with descriptions
4. Pass/Fail when run
4. Self-checking

The tests are for documentation and transparency and create a kind of audit trail - that's in addition to their role in correctness!
The test benches are for documentation and transparency and create a kind of audit trail - that's in addition to their role in correctness!

The tests give a Pass/Fail result, using an "assert", logging a failure message if the stated condition is not met. They are not just doing a demonstration run of the device, with a waveform output. See more details in the Validation Contract and in the project code.
Self-checking: Each test gives a Pass/Fail result. It does this by using an "assert" statement, that logs a failure message if the stated condition (at the output) is not met. The tests are not just doing a demonstration run of the device by way of a waveform output - although they do that also.

You have to "trust but verify" when scaling up a hardware design from lower-layer components. Test coverage will continue at the highest standard as the library expands going forward.
</details>

#### Validation Contract

The stamp of approval comes from the test bench code, but more is involved: Scripts and templates generate the code files of IceChips, and also ensure they are validated reliably and completely.
IceChips is actually built around validation end-to-end. The code files are generated by script, from a template, and all the working parts come together to ensure the Verilog is validated reliably and completely.

Here's an overview, with a visual showing the structure of the code files:

&ensp;&ensp;[Validation scheme](docs/validation-scheme.md) · How the the code files and .ice components are validated
&ensp;&ensp;[Validation scheme and contract](docs/validation-scheme.md) for the Verilog code files and the .ice components

&ensp;&ensp;[Direct to contract](docs/validation-scheme.md#the-contract)

Some nerdy stuff is included, by intention, such as [guidelines around test benches](docs/validation-scheme.md#what-is-a-good-test-bench) for open source purposes and community contribution.

#### Running the tests on your machine

Expand Down Expand Up @@ -161,6 +173,8 @@ The following keywords are related to PCBs and are **not** part of the present w

[FPGAwars list of projects][link-fpgawarsp] developed with Open Source FPGAs, including CPUs

[OSHWA][link-oshwa] · Open Source Hardware Association and their project list

## Acknowledgments

Juan González-Gómez [@Obijuan], Jesús Arroyo Torrens, Salvador E. Tropea, Democrito · for Icestudio collections
Expand All @@ -187,9 +201,9 @@ Marcus Lindholm · SVG graphic design help

[www.doulos.com/knowhow](https://www.doulos.com/knowhow/verilog_designers_guide/sequential_always_blocks) · intro to design and concepts in Verilog

[www.verilogpro.com](https://www.verilogpro.com/verilog-generate-configurable-rtl) · specific intro to generate loops and elaboration
[www.verilogpro.com](https://www.verilogpro.com/verilog-generate-configurable-rtl) · intro to generate loops and elaboration

#### Supporting open source technology:
#### The supporting open source technology:

[Icestudio][link-icestudio] and Apio built on top of IceStorm, Yosys, Arachne-pnr

Expand All @@ -211,6 +225,9 @@ Marcus Lindholm · SVG graphic design help
[link-openfpgat]: https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki
[link-fpgawars]: https://fpgawars.github.io
[link-fpgawarsp]: https://fpgawars.github.io/#projects
[link-oshwa]: https://certification.oshwa.org/directory.html
[link-maker]: https://en.wikipedia.org/wiki/Maker_culture
[link-makerf]: https://makerfaire.com
[link-wiki-7400]: https://en.wikipedia.org/wiki/List_of_7400_series_integrated_circuits
[link-wiki-synth]: https://en.wikipedia.org/wiki/Logic_synthesis
[link-web-comb-seq]: https://www.google.com/search?q=Combinational+versus+Sequential+Circuit
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## Buffers, Inverters
[7404](source-7400/7404.v) Hex inverter<br>
[7407](source-7400/7407.v) Hex buffer/driver (OC)<br>
[7404](source-7400/7404.v) Hex inverter<br />
[7407](source-7400/7407.v) Hex buffer/driver (OC)<br />

## Gates
[7400](source-7400/7400.v) Quad 2-input NAND gate<br>
[7402](source-7400/7402.v) Quad 2-input NOR gate<br>
[7408](source-7400/7408.v) Quad 2-input AND gate<br>
[7432](source-7400/7432.v) Quad 2-input OR gate<br>
[7486](source-7400/7486.v) Quad 2-input XOR gate<br>
[74266](source-7400/74266.v) Quad 2-input XNOR gate (OC)<br>
[7400](source-7400/7400.v) Quad 2-input NAND gate<br />
[7402](source-7400/7402.v) Quad 2-input NOR gate<br />
[7408](source-7400/7408.v) Quad 2-input AND gate<br />
[7432](source-7400/7432.v) Quad 2-input OR gate<br />
[7486](source-7400/7486.v) Quad 2-input XOR gate<br />
[74266](source-7400/74266.v) Quad 2-input XNOR gate (OC)<br />

## Gates - 3 or More Inputs
[7410](source-7400/7410.v) Triple 3-input NAND gate<br>
[7411](source-7400/7411.v) Triple 3-input AND gate<br>
[7420](source-7400/7420.v) Dual 4-input NAND gate<br>
[7421](source-7400/7421.v) Dual 4-input AND gate<br>
[7427](source-7400/7427.v) Triple 3-input NOR gate<br>
[7430](source-7400/7430.v) 8-input NAND gate<br>
[74260](source-7400/74260.v) Dual 5-input NOR gate<br>
[7410](source-7400/7410.v) Triple 3-input NAND gate<br />
[7411](source-7400/7411.v) Triple 3-input AND gate<br />
[7420](source-7400/7420.v) Dual 4-input NAND gate<br />
[7421](source-7400/7421.v) Dual 4-input AND gate<br />
[7427](source-7400/7427.v) Triple 3-input NOR gate<br />
[7430](source-7400/7430.v) 8-input NAND gate<br />
[74260](source-7400/74260.v) Dual 5-input NOR gate<br />

## Decoders
[7442](source-7400/7442.v) BCD to decimal one-of-ten decoder<br>
[7442](source-7400/7442.v) BCD to decimal one-of-ten decoder<br />

## Encoders
[74147](source-7400/74147.v) 10-line to 4-line priority encoder<br>
[74148](source-7400/74148.v) 8-line to 3-line priority encoder<br>
[74147](source-7400/74147.v) 10-line to 4-line priority encoder<br />
[74148](source-7400/74148.v) 8-line to 3-line priority encoder<br />

## Demultiplexers
[74138](source-7400/74138.v) 3-line to 8-line decoder/demultiplexer (inverted outputs)<br>
[74139](source-7400/74139.v) Dual 2-line to 4-line decoder/demultiplexer (inverted outputs)<br>
[74154](source-7400/74154.v) 4-line to 16-line decoder/demultiplexer (inverted outputs)<br>
[74155](source-7400/74155.v) Dual 2-line to 4-line decoder/demultiplexer (inverted outputs)<br>
[74238](source-7400/74238.v) 3-line to 8-line decoder/demultiplexer (active high outputs)<br>
[74138](source-7400/74138.v) 3-line to 8-line decoder/demultiplexer (inverted outputs)<br />
[74139](source-7400/74139.v) Dual 2-line to 4-line decoder/demultiplexer (inverted outputs)<br />
[74154](source-7400/74154.v) 4-line to 16-line decoder/demultiplexer (inverted outputs)<br />
[74155](source-7400/74155.v) Dual 2-line to 4-line decoder/demultiplexer (inverted outputs)<br />
[74238](source-7400/74238.v) 3-line to 8-line decoder/demultiplexer (active high outputs)<br />

## Multiplexers
[74150](source-7400/74150.v) 16-input multiplexer<br>
[74151](source-7400/74151.v) 8-input multiplexer<br>
[74153](source-7400/74153.v) Dual 4-input multiplexer<br>
[74157](source-7400/74157.v) Quad 2-input multiplexer<br>
[74158](source-7400/74158.v) Quad 2-input multiplexer (inverted outputs)<br>
[74352](source-7400/74352.v) Dual 4-input multiplexer (inverted outputs)<br>
[74150](source-7400/74150.v) 16-input multiplexer<br />
[74151](source-7400/74151.v) 8-input multiplexer<br />
[74153](source-7400/74153.v) Dual 4-input multiplexer<br />
[74157](source-7400/74157.v) Quad 2-input multiplexer<br />
[74158](source-7400/74158.v) Quad 2-input multiplexer (inverted outputs)<br />
[74352](source-7400/74352.v) Dual 4-input multiplexer (inverted outputs)<br />

## Comparators, Adders, Arithmetic Logic Units
[7485](source-7400/7485.v) 4-bit magnitude comparator<br>
[74283](source-7400/74283.v) 4-bit binary full adder with fast carry<br>
[7485](source-7400/7485.v) 4-bit magnitude comparator<br />
[74283](source-7400/74283.v) 4-bit binary full adder with fast carry<br />

## Flip-Flops
[7473](source-7400/7473.v) Dual J-K flip-flop with clear; negative-edge-triggered<br>
[7474](source-7400/7474.v) Dual D flip-flop with set and clear; positive-edge-triggered<br>
[74112](source-7400/74112.v) Dual J-K flip-flop with set and clear; negative-edge-triggered<br>
[7473](source-7400/7473.v) Dual J-K flip-flop with clear; negative-edge-triggered<br />
[7474](source-7400/7474.v) Dual D flip-flop with set and clear; positive-edge-triggered<br />
[74112](source-7400/74112.v) Dual J-K flip-flop with set and clear; negative-edge-triggered<br />

## Flip-Flops - Registers
[74273](source-7400/74273.v) Octal D flip-flop with clear<br>
[74377](source-7400/74377.v) Octal D flip-flop with enable<br>
## Registers
[74273](source-7400/74273.v) Octal D flip-flop with clear<br />
[74377](source-7400/74377.v) Octal D flip-flop with enable<br />

## Counters
[74160](source-7400/74160.v) 4-bit BCD decade counter with parallel load, asynchronous clear<br>
[74161](source-7400/74161.v) 4-bit modulo 16 binary counter with parallel load, asynchronous clear<br>
[74162](source-7400/74162.v) 4-bit BCD decade counter with parallel load, synchronous clear<br>
[74163](source-7400/74163.v) 4-bit modulo 16 binary counter with parallel load, synchronous clear<br>
[74160](source-7400/74160.v) 4-bit BCD decade counter with parallel load, asynchronous clear<br />
[74161](source-7400/74161.v) 4-bit modulo 16 binary counter with parallel load, asynchronous clear<br />
[74162](source-7400/74162.v) 4-bit BCD decade counter with parallel load, synchronous clear<br />
[74163](source-7400/74163.v) 4-bit modulo 16 binary counter with parallel load, synchronous clear<br />
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