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fix WS (1->2 by 48Mhz)
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xeno27 committed Jun 6, 2023
1 parent a679dbe commit 569c1d8
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions src/init_samd51.c
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
#include "uf2.h"

void system_init(void) {
/* Set 1 Flash Wait State for 48MHz */
NVMCTRL->CTRLA.reg |= NVMCTRL_CTRLA_RWS(0);
/* Set 2 Flash Wait State for 48MHz , refer to TAB 56.6 in datasheet*/
NVMCTRL->CTRLA.reg |= NVMCTRL_CTRLA_RWS(2);

// Output GCLK0 to Metro M4 D5. This way we can see if/when we mess it up.
//PORT->Group[1].PINCFG[14].bit.PMUXEN = true;
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