daq2: Parameterize JESD204 configuration values

Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <[email protected]>
analogdevicesinc · Jan 20, 2022 · 530aca9 · 530aca9
1 parent f3cf750
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Showing 5 changed files with 119 additions and 22 deletions.
diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl
@@ -1,25 +1,34 @@
+#
+# Parameter description:
+#   [RX/TX]_JESD_M : Number of converters per link
+#   [RX/TX]_JESD_L : Number of lanes per link
+#   [RX/TX]_JESD_S : Number of samples per frame
+#
 
 source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
 source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
 
 # JESD204B interface configurations
 
-set TX_NUM_OF_LANES 4           ; # L
-set TX_NUM_OF_CONVERTERS 2      ; # M
-set TX_SAMPLES_PER_FRAME 1      ; # S
-set TX_SAMPLE_WIDTH 16          ; # N/NP
+set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L)           ; # L
+set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M)      ; # M
+set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S)      ; # S
+set TX_SAMPLE_WIDTH 16                                      ; # N/NP
 set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
 
 set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
 
-set RX_NUM_OF_LANES 4           ; # L
-set RX_NUM_OF_CONVERTERS 2      ; # M
-set RX_SAMPLES_PER_FRAME 1      ; # S
-set RX_SAMPLE_WIDTH 16          ; # N/NP
+set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L)           ; # L
+set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M)      ; # M
+set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S)      ; # S
+set RX_SAMPLE_WIDTH 16                                      ; # N/NP
 set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
 
 set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
 
+set MAX_TX_NUM_OF_LANES 4
+set MAX_RX_NUM_OF_LANES 4
+
 # dac peripherals
 
 ad_ip_instance axi_adxcvr axi_ad9144_xcvr [list \
@@ -36,9 +45,9 @@ adi_tpl_jesd204_tx_create axi_ad9144_tpl $TX_NUM_OF_LANES \
                                          $TX_SAMPLE_WIDTH \
 
 ad_ip_instance util_upack2 axi_ad9144_upack [list \
-  NUM_OF_CHANNELS 2 \
-  SAMPLES_PER_CHANNEL 4 \
-  SAMPLE_DATA_WIDTH 16 \
+  NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
+  SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
+  SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
 ]
 
 ad_ip_instance axi_dmac axi_ad9144_dma [list \
@@ -118,8 +127,8 @@ ad_connect axi_ad9680_offload/sync_ext GND
 # shared transceiver core
 
 ad_ip_instance util_adxcvr util_daq2_xcvr [list \
-  RX_NUM_OF_LANES $RX_NUM_OF_LANES \
-  TX_NUM_OF_LANES $TX_NUM_OF_LANES \
+  RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES \
+  TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES \
   QPLL_REFCLK_DIV 1 \
   QPLL_FBDIV_RATIO 1 \
   QPLL_FBDIV 0x30 \
@@ -144,7 +153,7 @@ ad_xcvrpll  axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_*
 
 # connections (dac)
 
-ad_xcvrcon  util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd {0 2 3 1}
+ad_xcvrcon  util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd {0 2 3 1} {} {} $MAX_TX_NUM_OF_LANES
 ad_connect  util_daq2_xcvr/tx_out_clk_0 axi_ad9144_tpl/link_clk
 ad_connect  axi_ad9144_jesd/tx_data axi_ad9144_tpl/link
 ad_connect  util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/clk
@@ -172,7 +181,7 @@ ad_connect axi_ad9144_offload/s_axis axi_ad9144_dma/m_axis
 
 # connections (adc)
 
-ad_xcvrcon  util_daq2_xcvr axi_ad9680_xcvr axi_ad9680_jesd
+ad_xcvrcon  util_daq2_xcvr axi_ad9680_xcvr axi_ad9680_jesd {} {} {} $MAX_RX_NUM_OF_LANES
 ad_connect  util_daq2_xcvr/rx_out_clk_0 axi_ad9680_tpl/link_clk
 ad_connect  axi_ad9680_jesd/rx_sof axi_ad9680_tpl/link_sof
 ad_connect  axi_ad9680_jesd/rx_data_tdata axi_ad9680_tpl/link_data
@@ -234,4 +243,3 @@ ad_cpu_interrupt ps-10 mb-15 axi_ad9144_jesd/irq
 ad_cpu_interrupt ps-11 mb-14 axi_ad9680_jesd/irq
 ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq
 ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
-
diff --git a/projects/daq2/kc705/system_project.tcl b/projects/daq2/kc705/system_project.tcl
@@ -3,7 +3,28 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project daq2_kc705
+# get_env_param retrieves parameter value from the environment if exists,
+# other case use the default value
+#
+#   Use over-writable parameters from the environment.
+#
+#    e.g.
+#      make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 
+
+# Parameter description:
+#   [RX/TX]_JESD_M : Number of converters per link
+#   [RX/TX]_JESD_L : Number of lanes per link
+#   [RX/TX]_JESD_S : Number of samples per frame
+
+adi_project daq2_kc705 0 [list \
+  RX_JESD_M    [get_env_param RX_JESD_M    2 ] \
+  RX_JESD_L    [get_env_param RX_JESD_L    4 ] \
+  RX_JESD_S    [get_env_param RX_JESD_S    1 ] \
+  TX_JESD_M    [get_env_param TX_JESD_M    2 ] \
+  TX_JESD_L    [get_env_param TX_JESD_L    4 ] \
+  TX_JESD_S    [get_env_param TX_JESD_S    1 ] \
+]
+
 adi_project_files daq2_kc705 [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
@@ -13,4 +34,6 @@ adi_project_files daq2_kc705 [list \
 
 adi_project_run daq2_kc705
 
+## To improve timing in the axi_ad9680_offload component
+set_property strategy Performance_Retiming [get_runs impl_1]
 
diff --git a/projects/daq2/kcu105/system_project.tcl b/projects/daq2/kcu105/system_project.tcl
@@ -3,7 +3,28 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project daq2_kcu105
+# get_env_param retrieves parameter value from the environment if exists,
+# other case use the default value
+#
+#   Use over-writable parameters from the environment.
+#
+#    e.g.
+#      make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 
+
+# Parameter description:
+#   [RX/TX]_JESD_M : Number of converters per link
+#   [RX/TX]_JESD_L : Number of lanes per link
+#   [RX/TX]_JESD_S : Number of samples per frame
+
+adi_project daq2_kcu105 0 [list \
+  RX_JESD_M    [get_env_param RX_JESD_M    2 ] \
+  RX_JESD_L    [get_env_param RX_JESD_L    4 ] \
+  RX_JESD_S    [get_env_param RX_JESD_S    1 ] \
+  TX_JESD_M    [get_env_param TX_JESD_M    2 ] \
+  TX_JESD_L    [get_env_param TX_JESD_L    4 ] \
+  TX_JESD_S    [get_env_param TX_JESD_S    1 ] \
+]
+
 adi_project_files daq2_kcu105 [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
@@ -16,4 +37,3 @@ set_property strategy Performance_Retiming [get_runs impl_1]
 
 adi_project_run daq2_kcu105
 
-
diff --git a/projects/daq2/zc706/system_project.tcl b/projects/daq2/zc706/system_project.tcl
@@ -3,7 +3,28 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project daq2_zc706
+# get_env_param retrieves parameter value from the environment if exists,
+# other case use the default value
+#
+#   Use over-writable parameters from the environment.
+#
+#    e.g.
+#      make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 
+
+# Parameter description:
+#   [RX/TX]_JESD_M : Number of converters per link
+#   [RX/TX]_JESD_L : Number of lanes per link
+#   [RX/TX]_JESD_S : Number of samples per frame
+
+adi_project daq2_zc706 0 [list \
+  RX_JESD_M    [get_env_param RX_JESD_M    2 ] \
+  RX_JESD_L    [get_env_param RX_JESD_L    4 ] \
+  RX_JESD_S    [get_env_param RX_JESD_S    1 ] \
+  TX_JESD_M    [get_env_param TX_JESD_M    2 ] \
+  TX_JESD_L    [get_env_param TX_JESD_L    4 ] \
+  TX_JESD_S    [get_env_param TX_JESD_S    1 ] \
+]
+
 adi_project_files daq2_zc706 [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
@@ -14,4 +35,7 @@ adi_project_files daq2_zc706 [list \
 
 adi_project_run daq2_zc706
 
+## To improve timing in the axi_ad9680_offload component
+set_property strategy Performance_Retiming [get_runs impl_1]
+
 
diff --git a/projects/daq2/zcu102/system_project.tcl b/projects/daq2/zcu102/system_project.tcl
@@ -3,7 +3,28 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-adi_project daq2_zcu102
+# get_env_param retrieves parameter value from the environment if exists,
+# other case use the default value
+#
+#   Use over-writable parameters from the environment.
+#
+#    e.g.
+#      make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 
+
+# Parameter description:
+#   [RX/TX]_JESD_M : Number of converters per link
+#   [RX/TX]_JESD_L : Number of lanes per link
+#   [RX/TX]_JESD_S : Number of samples per frame
+
+adi_project daq2_zcu102 0 [list \
+  RX_JESD_M    [get_env_param RX_JESD_M    2 ] \
+  RX_JESD_L    [get_env_param RX_JESD_L    4 ] \
+  RX_JESD_S    [get_env_param RX_JESD_S    1 ] \
+  TX_JESD_M    [get_env_param TX_JESD_M    2 ] \
+  TX_JESD_L    [get_env_param TX_JESD_L    4 ] \
+  TX_JESD_S    [get_env_param TX_JESD_S    1 ] \
+]
+
 adi_project_files daq2_zcu102 [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
@@ -13,4 +34,5 @@ adi_project_files daq2_zcu102 [list \
 
 adi_project_run daq2_zcu102
 
-
+## To improve timing in the axi_ad9680_offload component
+set_property strategy Performance_Retiming [get_runs impl_1]