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adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS …
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…settings

Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
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@ronagyl
ronagyl committed Feb 18, 2021
1 parent 7c86b9f commit f45d5d9
Showing 1 changed file with 6 additions and 4 deletions.
10 changes: 6 additions & 4 deletions projects/adrv9001/zcu102/cmos_constr.xdc
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Original file line number Diff line number Diff line change
Expand Up @@ -47,8 +47,10 @@ create_clock -name rx2_dclk_out -period 12.5 [get_ports rx2_dclk_in_p]
create_clock -name tx1_dclk_out -period 12.5 [get_ports tx1_dclk_in_p]
create_clock -name tx2_dclk_out -period 12.5 [get_ports tx2_dclk_in_p]

set_clock_latency -source -early 2 [get_clocks rx1_dclk_out]
set_clock_latency -source -early 2 [get_clocks rx2_dclk_out]
set_clock_latency -source -early -0.25 [get_clocks rx1_dclk_out]
set_clock_latency -source -early -0.25 [get_clocks rx2_dclk_out]

set_clock_latency -source -late 0.25 [get_clocks rx1_dclk_out]
set_clock_latency -source -late 0.25 [get_clocks rx2_dclk_out]


set_clock_latency -source -late 5 [get_clocks rx1_dclk_out]
set_clock_latency -source -late 5 [get_clocks rx2_dclk_out]

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