dts: zynqmp-zcu102-rev10-ad9082-204c-txmode36-rxmode28: New use case

204C use case with Subclass 1, Med. lane rate, using gearbox and PRGOGDIV * 1Txs / 1Rxs per MxFE * DAC_CLK = 3.84 GSPS * ADC_CLK = 3.84 GSPS * Tx I/Q Rate: 3.84 GSPS (Interpolation of 1x1) * Rx I/Q Rate: 3.84 GSPS (Decimation of 1x1) * DAC JESD204B: Mode 36, L=8, M=2, N=N'=12 * ADC JESD204B: Mode 28, L=8, M=2, N=N'=12 * DAC-Side JESD204C Lane Rate: 11.88Gbps * ADC-Side JESD204C Lane Rate: 11.88Gbps Signed-off-by: Laszlo Nagy <[email protected]>
analogdevicesinc · Aug 26, 2022 · 3fc354a · 3fc354a
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diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9082-204c-txmode36-rxmode28-tplw6.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9082-204c-txmode36-rxmode28-tplw6.dts
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+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Analog Devices AD9082-FMC-EBZ
+ * https://wiki.analog.com/resources/eval/user-guides/quadmxfe/quick-start
+ * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081
+ *
+ * hdl_project: <ad9082_fmca_ebz/zcu102>
+ * board_revision: <>
+ *
+ * Copyright (C) 2022 Analog Devices Inc.
+ */
+
+// 204C use case with Subclass 1,
+// Med. lane rate, using gearbox and PRGOGDIV
+//     * 1Txs / 1Rxs per MxFE
+//     * DAC_CLK = 3.84 GSPS
+//     * ADC_CLK = 3.84 GSPS
+//     * Tx I/Q Rate: 3.84 GSPS (Interpolation of 1x1)
+//     * Rx I/Q Rate: 3.84 GSPS (Decimation of 1x1)
+//     * DAC JESD204B: Mode 36, L=8, M=2, N=N'=12
+//     * ADC JESD204B: Mode 28, L=8, M=2, N=N'=12
+//     * DAC-Side JESD204C Lane Rate: 11.88Gbps
+//     * ADC-Side JESD204C Lane Rate: 11.88Gbps
+//
+// Transport Layer Width 6 octets  (link layer gerbox ration 8:6)
+//
+
+// HDL Synthesis Parameters:
+// JESD_MODE=64B66B \
+// RX_RATE=12 \
+// TX_RATE=12 \
+// RX_JESD_M=2 \
+// RX_JESD_L=8 \
+// RX_JESD_S=8 \
+// RX_JESD_NP=12 \
+// RX_TPL_WIDTH=6 \
+// TX_JESD_M=2 \
+// TX_JESD_L=8 \
+// TX_JESD_S=8 \
+// TX_JESD_NP=12 \
+// TX_TPL_WIDTH=6
+
+#include "zynqmp-zcu102-rev10-ad9082-204c-txmode36-rxmode28.dts"
+
+&hmc7044 {
+
+		hmc7044_c6: channel@6 {
+			reg = <6>;
+			adi,extended-name = "CORE_CLK_TX";
+			adi,divider = <12>;  // 240 MHz
+			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
+		};
+
+		hmc7044_c10: channel@10 {
+			reg = <10>;
+			adi,extended-name = "CORE_CLK_RX_ALT";
+			adi,divider = <12>; // 240 MHz
+			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
+		};
+};
+