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plutosdr-fw: Update to 2018_R2 release and move to Vivado 2018.2
Swithched to the arm-linux-gnueabihf-gcc hard-float toolchain.
Implemented workaround for broken write sysdef.
Submodule buildroot 04dceb2..fea212a:
> configs/zynq_pluto_defconfig: Switch to HF toolchain found in Vivado 2018.2
> package/libiio/libiio.mk: Bump to Version 0.16
> board/m2k/post-build.sh: Add update firmware script
> configs/zynq_m2k_defconfig: Switch to arm-linux-gnueabihf toolchain
Submodule hdl d79ca23...401395c:
> adrv9009: A10GX: Initial commit
> a10soc: Common, increase SPI frequency to 10MHz
> adrv9009: A10SOC: Add second observation channel
> axi_adrv9009: Split DATAPATH parameter in multiple parameters for Intel IP
> a10soc: set "FORCE ALL USED TILES TO HIGH SPEED"
> adrv9009: A10SOC: Initial commit
> axi_adxcvr: Fix typo in initial parameters values
> axi/util_adxcvr: Add register to control eyescan reset
> axi_adxcvr: axi_adxcvr_es.v cleanup trailing whitespaces
> axi_adxcvr: Fix eyescan support for ultrascale plus devices
> axi_dmac/tb: Add support for xsim
> Add missing timescale annotations
> Remove Xilinx 6 series support
> axi_ad9361: Mark rst output as active high
> util_dacfifo: Delete unused registers
> util_dacfifo: Update constraint file
> ad_ip_jesd204_tpl_dac: Use perfect shuffle helper module
> library: Add perfect shuffle module
> util_dacfifo: Align the dac_xfer_out to the first valid data
> util_dacfifo: Update the dma_ready generation
> adrv9009/zcu102: Increase DAC buffer depth to 18Mb
> util_dacfifo: Simplify the write into buffer validation
> util_dacfifo: Fix the reset logic of the module
> util_dacfifo: Update the bypass logic
> util_dacfifo_bypass: The FIFO in this module is for CDC only, no need to have a large depth
> axi_dacfifo: Move util_dacfifo_bypass module to util_dacfifo IP
> axi_ad6676: Support multiple lane configuration
> axi_ad6676: Cosmetic update only
> axi_ad6676: Support multiple lane configuration
> adrv9371/zcu102: Tune the differential swing of the TX lines
> daq3/zcu102: Add custom configuration for CPLL
> util_adxcvr: Expose QPLL and CPLL *_CFG attributes
> util_adxcvr: Update GHTE4 input port from the wizard
> axi|util_adxcvr: Expose TX configurable driver ports
> interfaces_ip.tcl: Delete trailing white spaces
> util_adxcvr: Define all GTHE4 attribute in binary
> adrv9009/zcu102: Update initial configuration for GT clock output control
> util_adxcvr_xch: GTHE4 connect CPLL_FBDIV_45 attribute
> Revert "util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate"
> all/system_top.v: loopback gpio lines
> adi_project.tcl: Update the ZCU102 board preset version
> axi_hdmi_tx: Associate vdma_clk to s_axis interface
> fmcomms2/zc702: Modify implementation strategy to Performance Exlpore
> daq2_kcu105: Change implementation strategy
> zed, zc702, zc706, ccfmc: Send video trough axis interface
> axi_hdmi_tx: Create s_axis interface
> axi_dmac: fix transfer start synchronization
> adi_board.tcl: ad_xcvrcon: Fix width of sync port for multi-link setups
> axi_adcfifo: Fix constraints to apply also to Ultrascale devices
> axi_dmac: assert xfer_request only when ready
> axi_dmac: component level testbench updates
> axi_dmac: early abort 2d support
> axi_dmac: early abort support
> axi_dmac: request generator reworked to use FSM
> axi_dmac: preparation work for reporting length of partial transfers
> axi_dmac: drive destination eot from source side
> axi_dmac: wire destination descriptor through source
> fmcomms2:kcu105: Performance_ExploreWithRemap fixes DDR timing violation
> fmcadc2: VC707, specifically connect spi_csn[2:0] to the fmcadc2_spi module
> fmcomms2: cleanup system_top for kc705,kcu105, vc707 and zcu102
> motcon2_fmc: Remove muxaddr_out, refclk and refclk_rst from system_bd
> Add generated files for Intel projects to .gitignore
> axi_jesd204_tx: Fix multi-link constraints
> ad_dds_2: Don't try to round if signal is not truncated
> adi_ip_alt: ad_ip_create: Use 'description' for the DISPLAY_NAME propery
> daq3:kcu105: Performance_ExploreWithRemap results the highest WNS
> adrv9371x:kcu105: Performance_Retiming results the highest WNS
> m2k: Downgrade SPI related critical warning, as we use lower clock speed for power reasons
> axi|util_adxcvr: Delete reset interface inference for PLL resets
> sys_gen: Remove deprecated script
> util_gmii_to_rgmii: Fix ip.tcl script
> adi_project_alt: Update Quartus version to 18.0.0
> adi_board/adi_ip: Update Vivado version to 2018.2
> ad_ip_jesd204_tpl_dac: Add Platform Designer presets
> ad_ip_jesd204_tpl_dac: hw.tcl: Add mode validation
> ad_ip_jesd204_dac_tpl: hw.tcl: Add framer input information parameters
> ad_ip_jesd204_tpl_dac: hw.tcl: Choose lowest latency SAMPLES_PER_FRAME value
> ad_ip_jesd204_tpl_dac: Add support for modes with N or N' != 16
> ad_ip_jesd204_tpl_dac: Make framer more flexible
> ad_ip_jesd204_tpl_dac: Add Xilinx IP Integrator GUI integration
> ad_ip_jesd204_tpl_dac: Add Intel Platform Designer GUI integration
> ad_ip_jesd204_tpl_dac: Removed unused clk signal from framer module
> axi_ad91{44,52}: hw.tcl: Add missing file
> daq3: ZCU102: Remove Offload FIFO for ADC path.
> util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate
> daq3: ZCU102: Fixed system_top to be similar with ZC706. Updated constraints to specify exactly transceiver pin locations
> fmcomms5/zcu102/system_constr.xdc: Fix typo
> common/daq2: Fix typo
> daq2/common: Add default util_adxcvr parameters
> axi_dmac: Reduce the width of ID signals to minimum
> axi_dmac: Use AXI3 for DMAC in Intel projects
> adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs
> util_adcfifo: Synchronize the ad_rst and use it as a synchronous reset
> adrv936x, fmcomms2/5, usrpe31x: Fix warning on the dac path
> axi_hdmi_tx: Update axi_hdmi_tx_hw.tcl to support the ADI VDMA
> adrv9361z7035/ccfmc: Replace VDMA with ADI DMAC
> common/zc702: Replace VDMA with ADI DMAC
> common/zc706: Replace VDMA with ADI DMAC
> common/zed_system_bd.tcl: Replace VDMA
> axi_hdmi_tx_vdma: Cosmetic update
> axi_hdmi_tx: Update to use ADI DMA
> ad_ip_jesd204_tpl_dac: Add interface definition for the link interface
> ad_ip_jesd204_tpl_dac: Fix pattern output correctly when DATA_PATH_WIDTH=1
> ad_ip_jesd204_tpl_dac: Share PN sequence generator between all channels
> ad_ip_jesd204_tpl_dac: Fix PN generator reset state
> ad_ip_jesd204_tpl_dac: Drop extra pipeline stage from the framer
> ad_ip_jesd204_tpl_dac: channel: Remove unused registers
> ad_ip_jesd204_tpl_dac: Remove unused parameter
> ad_ip_jesd204_tpl_dac: Drop DAC prefix from parameters
> ad_ip_jesd204_tpl_dac: hw.tcl: Use relative paths for local files
> ad_ip_jesd204_tpl_dac: hw.tcl: Fix typo
> common/mitx045: Remove carrier support
> Remove adv7511/common: Deprecated
> ad_rst: Synthesis attribute 'preserve' is redundant
> ad_rst: All the synchronization registers have to have ASYNC_REG TRUE
> daq3, fmcomms2/5: Cosmetic update only of the xdc files
> daq3,fmcomms2/5 on zcu102: Fix warnings
> adi_board.tcl: ad_ip_instance: Add support for specifying IP parameters
> all/system_top.v: drive unused gpio inputs with zero
> adrv936x/ccbox_lvds: unconnected clock for ad9361 input protection
> adrv9009/adrv9371x/fmcomms2:Drop usage of ad_iobuf on non-bidirectional IOs
> all: Drive undriven input signals, complete interface
> fmcadc4: Fix chip selects for ada4961 c,d channels
> axi_spdif_rx: clear warning
> ad_tdd_control: Register tdd_endof_frame
> ad_tdd_control: Delete redundant reset from tdd_burst_counter logic
> ad_tdd_control: Switch '> 0' to '!= 0' to improve design
> Remove interrupts from system_top for all xilinx projects
> ad_rst: Fix constraints for Intel designs
> adi_tquest: Improve the timing report generation
> ad_rst: Update SDC constraints of the module
> ad_rst: Initial value of the registers should be its default value
> axi_gpreg: Use the common ad_rst constraints
> ad_rst: Update all the modules, which instantiate the ad_rst
> ad_rst: Update the reset synchronizer module
> scripts/adi_project.tcl: Overrides the default individual msg limit to 2000
> ad_mem_asym: Improve the implementation of the asymmetric RAM
> adi_ip: Use 'associate_bus_interface' command to setup the clock and reset for s_axi
> adi_ip: Define the default driver value to 0 for unused ports
> adi_board.tcl: Update the VCC/GND instance generation
> fmcadc5: remove SYSREF from IOB
> jesd204: Check lane error count in register map testbench
> jesd204: Fix RX regmap testbench version ID
> jesd204: Fix loopback testbench
> axi_hdmi_tx: Added INTERFACE parameter for selecting the interface type
> jesd204_rx/tx: make SYSREF IOB placement optional
> axi_dmac: fix address width detection
> fmcomms5_zc702: Enable AXI_SLICE for the DMA
> axi_ad9371: Increase dds quality
> axi_ad9144: Increase dds quality
> axi_ad9122: Increase dds quality
> axi_ad9739a: Use polynomial DDS
> ad_dds: Fix synthesis updates
> ad_dds_2: Remove unused disable logic feature
> axi_ad9162: Updates for ad_dds phase acc wrapper
> axi_ad9152: Updates for ad_dds phase acc wrapper
> axi_adrv9009: Updates for ad_dds phase acc wrapper
> jesd204/ad_ip_jesd204_tpl_dac: Updates for ad_dds phase acc wrapper
> axi_ad9963: Updates for ad_dds phase acc wrapper
> axi_ad9739a: Updates for ad_dds phase acc wrapper
> axi_ad9371: Updates for ad_dds phase acc wrapper
> axi_ad9361: Updates for ad_dds phase acc wrapper
> axi_ad9144: Updates for ad_dds phase acc wrapper
> axi_ad9122: Updates for ad_dds phase accumulator wrapper
> ad_dds: Add selectable phase width option.
> Add ad_dds.v
> Rename ad_dds.v to ad_dds_2.v
> ad_dds: Add selectable out data width and fair rounding
> ad_dds_1.v: Fully use the selectable data width feature
> ad_mul.v: Add parameters for A and B input widths
> ad_dds_sine_cordic: Fix sine pic to pic amplitude.
> ad_dds: Separated phase width from data width
> ad_dds_sine_cordic: Ajust for rounding errors
> ad_dds_cordic: Move the shifting operation
> ad_dds_sine: Cosmetic updates only
> ad_dds_cordic_pipe.v: Optimize for implementation
> ad_dds_sine_cordic.v: Suppress warning
> ad_dds_1.v: Fix concatenation width mismatch
> fmcomms2/common: Use DDS cordic on 14 bit atan LUT
> axi_ad9963:: Update for CORDIC algorithm
> axi_ad9739a: Update for CORDIC algorithm
> axi_ad9379: Update for CORDIC algorithm
> axi_ad9371: Update for CORDIC algorithm
> axi_ad9361: : Update for CORDIC algorithm
> axi_ad9162: Update for CORDIC algorithm
> axi_ad9152: Update for CORDIC algorithm
> axi_ad9144: Update for CORDIC algorithm
> axi_ad9122: Update for CORDIC algorithm integration
> ad_dds: Update for CORDIC algorithm integration
> ad_dds_1: Update for CORDIC algorithm integration
> ad_dds: Add sine generator using CORDIC algorithm
> adi_board.tcl: ad_xcvrcon: Add support for sparse PHY to link connections
> adi_board.tcl: ad_xcvrcon: Add option to specify device clock
> jesd204_rx: Count errors only once per character
> jesd204_rx: Reset lane error statistics when link is disabled
> axi_dmac: TLAST support for 2d transfers
> axi_dmac: fix 2d transfer address width
> axi_dmac: renamed .h files to .vh
> axi_dmac: ttcl file support for simulation
> axi_dmac: diagnostic interface in bursts
> axi_adrv9009: Use the correct clock for the observation path interface
> axi_dmac: Remove unused constraint
> axi_dmac: add tlast to the axis interface for Intel
> usrpe31x: Remove interrupt connections from system_top
> usrpe31x: Add the second channel
> usrpe31x: Initial commit
> axi_dmac: Enforce transfer length and stride alignments
> axi_dmac: Move transfer abort logic to data mover
> axi_dmac: Move sync transfer start logic to the data mover
> axi_dmac: Cleanup data mover
> axi_dmac: Remove backpressure from the source pipeline
> axi_dmac: Limit number of bursts on the source side
> axi_dmac: Remove second destination side register slice
> axi_dmac: Eliminate beat counter for the destination interfaces
> axi_dmac: Route destination request ID through the burst memory
> axi_dmac: Rework data store-and-forward buffer
> axi_dmac: dest_axi_mm: Simplify dependency management
> axi_dmac: Allow to disable FIFO interfaces immediately
> axi_dmac: Hook up rlast for MM-AXI source interface
> axi_dmac: Add testbenches that exercise DMA shutdown
> axi_dmac: Rework transfer shutdown
> axi_dmac: Split transfer handling into separate sub-module
> axi_adrv9009: Split DATAPATH parameter in multiple parameters. Map the parameters in the CONFIG register
> adrv9009: Added option for enabling the second observation channel
> axi_adrv9009: Added option for second observation channel
< daq3: ZCU102 project not supported in this release
> Move GTM projects to gtm_projects branch
> Remove projects we don't support anymore
< adv7511:mitx045: Remove, as it's not part of the release
< adv7511:ac701: Remove, as it's not part of the release
< cn0363:microzed: Remove, as it's not part of the release
< fmcomms2:mitx045: Remove, as it's not part of the release
< m2k:zed: Remove, as it's not part of the release
< imageon:zc706: Remove, as it's not part of the release
< ad7768evb: Remove, as it's not part of the release
< daq7980_sdz: Remove, as it's not part of the release
< ad77681evb: Remove, as it's not part of the release
< ad7616_sdz: Remove, as it's not part of the release
< ad738x_fmc: Remove, as it's not part of the release
< ad7134_fmc: Remove, as it's not part of the release
< ad5766_sdz: Remove, as it's not part of the release
> motcon2_fmc: Add additional clock constraints and set delays for ethernet
> motcon2_fmc: Connect GPO pins to controller 1
> motcon2_fmc: Sync transfer start for the current monitor DMAs
> motcon2_fmc: Ethernet MDIO set to EMIO
> motcon2_fmc: Update to revision C
< motcon2_fmc: Add additional clock constraints and set delays for ethernet
< motcon2_fmc: Connect GPO pins to controller 1
< motcon2_fmc: Sync transfer start for the current monitor DMAs
< motcon2_fmc: Ethernet MDIO set to EMIO
< motcon2_fmc: Update to revision C
> axi_dacfifo: Always use equal or not equal
> axi_dacfifo: Fix address buffer read logic
> axi_dacfifo: Counters must use 1'b1 for incrementation
> axi_dacfifo: Delete unused registers/nets
< axi_dacfifo: Always use equal or not equal
< axi_dacfifo: Fix address buffer read logic
< axi_dacfifo: Counters must use 1'b1 for incrementation
< axi_dacfifo: Delete unused registers/nets
> adi_tquest.tcl: Check recovery and and removal timing
> axi_dmac: Be more specific about debug register timing exceptions
< adrv9009: Throughput improvements
> adrv9009: Increased DMA clock frequency to ~333 MHz, by enabling AXI SLICES for DMAs
> adrv9009: Increase all DMAs MAX_BYTES_PER_BURST to 256
> adrv9009: Increase sys_dma_clk to 325MHz. At 333 MHz, there are timing violations
> adrv9009: Reduced DAC FIFO size, as it's not useful for real applications and the memory can be used in other parts of the design
> adrv9009: Increase DMA FIFO sizes
< util_dacfifo_bypass: Update comments
< _dacfifo: Fix the util_dacfifo_module
< axi_dacfifo: Cosmetic changes in util_dacfifo_bypass
< util_dacfifo: Fix gray coder/decoder
< axi_dacfifo: Remove unused signals
< axi_dacfifo: Add missing read-enable signal to ad_mem instance
> util_dacfifo_bypass: Update comments
> [axi|avl]_dacfifo: Fix the util_dacfifo_module
> axi_dacfifo: Cosmetic changes in util_dacfifo_bypass
> util_dacfifo: Fix gray coder/decoder
> jesd204: Update Makefiles
> Fixed typo
> axi_dacfifo: Remove unused signals
> axi_dacfifo: Add missing read-enable signal to ad_mem instance
> util_dacfifo: Reduce logic on high fan-out dma_wren_s signal
> daq3: ZCU102: Fix AXI_ADXCVR IPs XCVR_TYPE parameter
< daq3: ZCU102: Fix AXI_ADXCVR IPs XCVR_TYPE parameter
< de10: Remove, as it's not supported in this release
< fmcomms2: AC701: Remove, as it's not supported in this release
> util_cdc: Silence warnings about unused sequential logic
> daq2|3: Set up OPTIMIZATION_MODE to improve timing
< daq2|3: Set up OPTIMIZATION_MODE to improve timing
> axi_dmac: Revert EOT memory to FIFO structure
> axi_dmac: request_generator: Remove reset from data path
> axi_dmac: 2d_transfer: Remove resets from data path
> axi_dmac: address_generator: Remove resets from data path
> axi_dmac: Use localparam instead of parameter
> axi_dmac: Increase default store-and-forward memory size to 8 bursts
> axi_dmac: Use a more descriptive label for the store-and-forward memory size
> axi_dmac: List valid store-and-forward memory sizes
> axi_dmac: dest_axi_stream: Remove outdated comment
> zcu102: updated IOSTANDARD of Bank 44 IOs to match VCCO 3.3V
> fmcomms5: Delete unused GPIO lines from system top
> fmcjesdadc1: increase DMAC FIFO size
< fmcjesdadc1: increase DMAC FIFO size
< adrv9009: Removed ZC706 based project
> adrv9009: Removed ZC706 based project
> adrv9009: Improved data throughput and DAC FIFO size
< adrv9009: Improved data throughput and DAC FIFO size
> jesd204: Fix constraints for axi_jesd_tx
> jesd204: Add constraints for the rx statistics clock crossing
> jesd204: Add RX error statistics (#98)
> axi_dmac: Fix debug ID order
> jesd204:version: Increase version number fot TX
> jesd204:up_common: Add a synthesis register for NUM_LINKS
> jesd204:tx_ctrl: Update the sync_request logic
> jesd204:tx_ctrl: status_sync register contains the raw SYNC status
> jesd204:tx_ctrl: Fix sync_bits instance
> jesd204:up_common: Move cfg_links_disable to 0x086 address space
> jesd204:tb: Update test bench to support dynamic multi-link on TX side
> jesd204_tx: Add dynamic multi-link support
> jesd204:rx_ctrl: Fix the cfg_links_disable mask
> jesd204:version: Increase version number for RX
> jesd204:up_common: Add a synthesis register for NUM_LINKS
> jesd204:up_common: Move cfg_links_disable to 0x086 address space
> jesd204_tb: Update testbench to support dynamic multi-link on RX side
> jesd204_rx: Add dynamic multi-link support
> axi_dmac/dma_write_tb: added data integrity check
> axi_dmac: added ModelSim support to run_tb.sh
> axi_dmac: made vlog pass
> axi_dmac: Add transfer testbenches
> axi_dmac: Add simple register map testbench
> axi_dmac: Split register map into separate sub-module
> axi_dmac: axi_dmac_hw.tcl: Use ad_ip_files helper
> ad_ip_alt.tcl: ad_ip_addfile: Add support for header files
> axi_ad9144: Hide unused ports in DUAL mode
> axi_ad9144: Completely disable unused channels in DUAL mode
> axi_ad9152: Use the generic JESD204 DAC transmitter core
> axi_ad9144: Use the generic JESD204 DAC transmitter core
> library: Add a generic JESD204 DAC receiver core
> axi_ad9680: Use the generic JESD204 ADC receiver core
> axi_ad9250: Use the generic JESD204 ADC receiver core
> axi_ad6676: Use the generic JESD204 ADC receiver core
> ad_ip_jesd204_tpl_adc: Add IP definition file for Intel platforms
> library: Add a generic JESD204 ADC receiver core
> Remove unused DMA underflow signal from ADC DMA interface
> Remove unused DMA overflow signal from DAC DMA interfaces
< axi_dmac: Fix bus resize block reset
> xilinx: util_adxcvr: Add support for lane polarity inversion
> altera: jesd204: Add support for lane polarity inversion
> jesd204_soft_pcs_loopback_tb: Add parameter for lane polarity inversion
> jesd204_soft_pcs_tx: Add support for lane polarity inversion
> jesd204_soft_pcs_rx: Add support for lane polarity inversion
> axi_dmac: Fix bus resize block reset
Submodule linux 2398d50...0272a4d:
> arm64: dts: zynqmp-zcu102-rev10-adrv9375.dts: Add devicetree for AD9375
> iio: adc: ad9680: avoid duplicated error message (Sync with master)
> iio: adc: ad9361: Fix to prevent invalid RFBW setting during enable FIR
> iio: adc: adrv9009: Add missing FHM API to set the next hop frequency
> iio: adc: ad9680: maintain current sysref rate in case it's a fit
> arm: dts: zynq-e310.dts: Fix VCRX_V1,V2 GPIO inversion
> arch/arm64/configs/adi_zynqmp_defconfig: Add ADRV9008 firmware
> dmaengine: dmatest: add norandom option
> dmaengine: dmatest: Remove use of VLAs
> dmaengine: dmatest: fix container_of member in dmatest_callback
> dmaengine: dmatest: move callback wait queue to thread context
> dmaengine: dmatest: warn user when dma test times out
> Revert "dmatest: Fixed alignment issue with PL330 DMA driver for Zynq."
> iio: adc: ad9371: Fix spelling typo - no functional changes
> arm64: dts: Add device trees for ADRV9008-1 and ADRV9009-2 on ZCU102
> iio: adc: adrv9009: Add support for ADRV9008-1 and ADRV9008-2
> iio: adc: adrv9009: Fix get agc mode
> iio: adc: adrv9009: Fix error and roll-back handling in setup
> iio: adc: adrv9009: Be more verbose when clk_set_rate fails
> iio: jesd204: xilinx_transceiver: Add debug prints in cpll|qpll config
> dma: axi-dmac: terminate early DMA transfers after a partial one
> dma: axi-dmac: populate residue info for completed xfers
> dmaengine: virt-dma: store result on dma descriptor
> dma: axi-dmac: assign `copy_align` property
> iio: adc: ad9371: Fix error and roll-back handling in setup
> iio: adc: ad9371: Fix compiler warning
> iio: adc: ad9371: Be more verbose when clk_set_rate fails
> firmware/Mykonos_M3.bin: Update to Firmware Version 5.2.2
> drivers/iio/adc/mykonos: Update Mykonos API version: 1.5.2.3566
> Merge pull request #244 from analogdevicesinc/iio-adc-ad9361-fix-tdd-ext-lo
> iio: adc: ad9361: MGC maintain gain in case we cross a gaintable boundary
> iio: jesd204: axi_adxcvr_eyescan: Fix UltraScale+ GTH Eye Scan
> iio: frequency: ad9528: provide clocks uncached
> iio: jesd204: xilinx_transceiver: Be less verbose
> iio: adc: ad9371: Add support for setting the SYSREF rate
> iio: adc: adrv9009: Add support for setting the SYSREF rate
> Merge pull request #239 from analogdevicesinc/fix-arm64-adrv9009-reg-properties
> microblaze: dts: [vc707|kc705|kcu105]_fmcomms2-3.dts: Fix GPIO numbers
> dt-bindings: iio: adc: Add docs for ad400x
> dts: zynq-adv7511: ad4020: Add dts file
> iio: adc: ad400x: Add ad400x support
> spi: spi-axi-engine: Removed SLEEP command from offload message
> spi: spi-axi-engine: Fixed reset for offload
> spi-axi-engine: Calculate buffer dimension for xfer
> spi: spi-axi-engine: fix delay computation
> iio: adc: ad7768: Fix iio_buffer removal
> dts: arm[64]: Update adi,axi-adxcvr-1.0 device names
> iio: adc: ad9361: Fix out_voltage0_hardwaregain_available reading
> build,travis: split builds into smaller parts
> clk: adf4360: Add support for ADF4360-0 through ADF4360-9
> iio: ad9144: Add support for updating SYSREF frequency
> iio: ad9144: Add infrastructure for PLL support
> iio: frequency: ad9528: Add support for controlling the SYSREF rate
> dts: Add devicetree for AD9136-FMC-EBZ + Arria10 SoC
> dts: Add devicetree for AD9136-FMC-EBZ + ZC706
> iio: cf_axi_dds: Add device entry for AD9136
> iio: adc: adrv9009: Remove unhandled AGC modes
> iio: jesd204: xcvr: Avoid using DRP broadcast to prevent undesired behavior
> iio: buffer-dmaengine: Use min_t() for comparing integers of different types
> iio: buffer-dmaengine: Use %zu for size_t printf
> iio: buffer-dma: Fix warning about integer to pointer cast
> dts: arm64: Use 32-bit addresses for FPGA peripherals
> dts: Add missing vendor prefixes
> devicetree: Cleanup adi-*.dtsi
> Merge pull request #224 from analogdevicesinc/cleanup-dt-dma
> Merge pull request #223 from analogdevicesinc/fix-zynqmp-clk-memory-leak
> Merge pull request #222 from analogdevicesinc/fix-dwc3-4.14
> iio: buffer-dmaengine: Report buffer length requirements
> dts: fmcdaq3: Fix DMA channel description
> iio: jesd204: axi_jesd204_[rx|tx]: Status add LMFC rate
> iio: adc: ad_adc: Add compatible for single RX ADRV9009
> iio: adc: adrv9009: Fix loading of profiles which require ADC stitching
> arm64: dts: adi-adrv9009: FHM config use better defaults
> arm64: dts: adi-adrv9009: Increase adi,tx-pa-protection-tx-peak-threshold
> arm64: dts: Provide unique JESD204 and XCVR device names
> iio: adc: adrv9009: Fix dev_err() format string
> iio: jesd204: adi_xcvr: Add direct register access debug interface
> dt-bindings: iio: adc: Add docs for ad7124
> iio: adc: Add ad7124 support
> iio: jesd204: axi_adxcvr_eyescan: Allow eyescan cancel
> iio: ad9680: initialize `ret` var
> drivers: mathworks: fix printf format for size_t on 64 bit
> drivers: mathworks: fix iio buffer include
> build,.travis.yml: add compile test builds
> ci/travis: move yaml scripts into shell file
> iio: jesd204: axi_jesd204_[rx|tx]: Clear SYSREF status between link up/down
> iio: jesd204:axi_adxcvr_eyescan: XCVR add 2D statistical Eye Scan support
> iio: jesd204: axi_jesd204_tx: Return SYSREF disabled for Subclass 0 devices
> iio: jesd204:axi_jesd204_rx: Correct ILAS lane info parameters
> iio: adc: adrv9009: Handle <clkPllHsDiv=X.0> cases in parse profile
> iio: Remove buffer_impl.h include from buffer.h
> iio: inkern: Include buffer_impl.h instead of buffer.h
> iio: Use buffer_impl.h include where appropriate
> iio: Move iio_buffer_remove_sample() to buffer.h
> iio: Move iio_buffer_{free,alloc}_scanmask() to consumer.h
> iio: consumer.h: Add missing forward declaration for struct iio_buffer
> misc: mathworks: Fix copy size on 64-bit platforms
> drivers: mathworks: update PCI code
> iio: Fix scan mask selection
> iio: ad5064: Fix regulator handling
> Revert "iio: ad5064: Explicitly configure whether to use external supply"
> iio: adc: adrv9009: Fix get in_voltage1_gain_control_pin_mode_en for RX2
> axi_spi_engine: Add word length register command
> cec: remove cec-edid.c
> cec/v4l2: move V4L2 specific CEC functions to V4L2
> cec: integrate cec_validate_phys_addr() in cec-api.c
> cec: make cec_get_edid_spa_location() an inline function
> iio: core: fix enums with gaps
> ASoC: hdmi-codec: fix routing
> iio: axi_jesd204_{tx,rx}: Add missing Kconfig dependencies
> dma: axi-dmac: don't check the number of frames for alignment
> iio: dac: ad5758: Add support for hard reset
> dt-bindings: iio: dac: Add docs for AD5758 DAC
> iio: dac: Add AD5758 support
> iio: adxl372: Fix revid check
> arm64: dts: zcu102-fmcdaq2: Fix JESD interrupt numbers
> arm64: dts: Add FMCDAQ3 support for ZCU102
> arm64: dts: zcu102-fmcdaq2: Fix s_axi_aclk assignment
> dt-bindings: adxl372: Document the adxl372 I2C bindings
> iio: adxl372: Add support for I2C communication
> iio: adxl372: Refactor the driver
> drivers: mathworks: fix functions type for vm fault
> iio: adxl372: Align with upstream version
> regmap: Add regmap_noinc_read API
> drm: axi_hdmi_encoder: Expand colorspace range for RGB mode
> Merge remote-tracking branch 'adi/master-4.14'
> iio: dac: Add AD5600 support
> arm64: dts: zynqmp-zcu102-rev10-ad9361-fmcomms5.dts: Fix core name
> Value 0 for ADF5355 Phase Resync Clock Divider is "Not allowed" according to datasheet. Change to 1 which is "Normal Operation".
> dts: zynq-adv7511: Replace Xilinx VDMA with ADI AXI-DMAC
> dma: axi-dmac: Enable FLAG_LAST independent of FLAG_CYCLIC
> dma: axi-dmac: Add support for interleaved cyclic transfers
> drm: adi_axi_hdmi: Pass the CYCLIC flag to the DMA driver
> drm: adi_axi_hdmi: Remove the Xilinx constraint
> dma: axi-dmac: Enable DMA_INTERLEAVE capability
> iio: frequency: cf_axi_dds: Bypass PL DDR FIFO for non-cyclic transfers
> iio: adc: ad9371: Add support for set/get GPIO Monitor Out via debugfs
> iio: adc: ad9371: Add support for FIR, ADC and loopback profiles via dt
> iio: adc: ad9371: Mixed bag of compiler warning fixes
> Merge pull request #174 from analogdevicesinc/dev_ad9157_firmware_less
> iio: adc: ad9371: Fix warning ret might be used uninitialized
> iio: adc: adrv9009: Enable RX1/RX2 RSSI/Decimated Power Measurements
> iio: adc: adrv9009: Extend MCS checking for JESD SYSREF STAT
> iio: hmc7044: Add debug register access
> devicetree: bindings: Add documentation for HMC7044 driver
> iio: frequency: New driver for HMC7044
> iio: adc: adrv9009: Update firmware to Version 5.0.3
> iio: adc: adrv9009: Update to Talise API version: 3.5.0.2
> dts: ad936x: Enable TX LO power-down managed mode
> drivers: iio: ad9361: Introduce TX LO power-down managed mode
> drivers: iio: ad9361: Fix out_volatge_hardwaregain_available readings
> iio: axi_jesd204_rx: Add error statistics to lane status info
> iio: axi_jesd204_rx: Reduce axi_jesd204_rx_watchdog() indentation
> treewide: sync white-space with upstream
> [media] ad9389b: verify EDID header
> [media] ad9389b: retry setup if the state is inconsistent
> [media] ad9389b: remove rx-sense irq dependency
> configs: Enable ADXL372 driver in defconfigs
> iio:adxl372: Add filter bandwidth support
> iio:adxl372: Add sampling frequency support
> iio:adxl372: Add FIFO and interrupts support
> iio:buffer: Introduced a function to assign the buffer specific attrs.
> dt-bindings: iio: accel: Add docs for ADXL372
> iio: adxl372: New driver for Analog Devices ADXL372 Accelerometer
> zynq-zed-adv7511-ad7768.dts: add MCLK to the device-tree
> devicetree: iio: adc: AD7768: Add clock specifier
> iio: adc: AD7768: Add support sampling frequency configuration
> iio: axi_jesd204_rx: Use early buffer release in subclass 0 mode
> iio: Fix kfifo checks in iio_kfifo_remove_from
> iio: ad9508: Use device managed clk_register()
> iio: ad9508: Use DIV_ROUND_CLOSEST() when computing the phase
> iio: ad9508: Fix output channel phase calculation
> iio: ad9508: Fix clk_round_rate()
> io: ad9508: Enable PART_ID check
> iio: ad9508: Turn a few dev_info() into dev_dbg()
> iio: ad9508: Read clock output names from devicetree
> iio: ad9508: Remove stray #define DEBUG
> dma: axi-dmac: Discover length alignment requirement
> dt-bindings: iio: adc: Add docs for ad7768
> zynq-zed-adv7511-ad7768.dts: add reference DT for AD7768
> iio: adc: Add ad7768 preliminary driver
> iio: ad9144: Power-down unused DAC channels
> iio: ad9144: Add support for AD9135/AD9136
> iio: ad9144: Add support for all JESD204 modes
> iio: ad9144: Consider interpolation factor for maximum samplerate
> iio: ad9144: Apply SERDES optimization values for AD9152
> iio: ad9144: Update required device configuration writes
> iio: ad9144: Remove dead code
> iio: ad9144: Read full chip ID and chip grade
> iio: ad9144: Update SERDES band limits
> iio: ad9144: Add support for SPI 4-wire mode
> iio: ad9144: Perform reset before accessing other registers
> iio: ad9144: Remove DAQ3 early PCB workaround
> iio: ad9144: Add support for both TXEN pins
> iio: ad9528: Fix updating clock output rate
> dts: zynqmp-zcu102-rev10-adrv9009: Enable dual observation channels
> Revert "iio: adc: ad_adc: ADRV9009 temporarily revert 4 channel support"
> iio: frequency: adf5355: Fix ADF53555 inverted RFoutB enable logic
> iio: frequency: adf5355: Fix uninitialized variable usage
> iio: frequency: adf5355: Remove assignment without effect
< Merge branch 'master' into 2018_R1
< arch/arm/boot/dts/zynq-e310: Add EttusResearch E310 IIO Linux support
< arch: arm: sidekiqz2: adjust min rx/tx frequencies for filters
< arch: arm: sidekiqz2: remove unreachable filterbanks setting
< dt-bindings: adi,ad9361.txt: fix typo in doc for filter-banks control
< iio: adc: adrv9009: Add ADRV9009 wideband RF transceiver Linux device driver
< iio: adc: ad_adc: ADRV9009 temporarily revert 4 channel support
< iio: adc: ad_adc: Add support for ADRV9009
< iio: adc: cf_axi_adc_core: Add support for ADRV9009
< iio: frequency: cf_axi_dds: Add support for ADRV9009
< iio: adc: talise: Add Linux HAL
< iio: adc: talise: Reduce verboseness
< iio: adc: talise: Use kernel 64-bit divide primitives
< iio: adc: talise: Use proper kernel includes
< iio: adc: talise: Add unmodified ADI HAL
< iio: adc: talise: Import unmodified Talise Rel v4.0-RC4 API Version 3.4 driver
< firmware: Add Talise ADRV9009 Release v4.0-RC4 firmware files
< iio: jesd204: axi_jesd204_{rx,tx}: Store subclass version in the correct field
< Merge branch 'master' into 2018_R1
< Merge branch 'master' into 2018_R1
< Merge branch 'master' into 2018_R1
< drivers: iio: frequency: cf_axi_dds: Fix driver remove path
< drivers: iio: frequency: cf_axi_dds: Fix function return path
Submodule u-boot-xlnx f5f001e..89d0754:
> configs: zynq_m2k_defconfig: Set bootldelay 0
> board: xilinx: zynq: board: Optimize board_late_init
Signed-off-by: Michael Hennerich <[email protected]>- Loading branch information
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