PlutoSDR: Prepare for v0.35 release

Submodule buildroot 35af596..19749a3:
  > package: libiio: libiio.mk: Bump libiio to version 0.24
  > pluto-sdr: enable easy updating of firmware from github
  > package/libiio: Update to the latest git HEAD and add HWMON support
  > package/libm2k: Bump to version 0.6.0 and avoid github dl issue
  > linux/linux.mk: Copy simpleImage ELF to output dir
  > configs/microblaze_adi_defconfig: Misc updates
  > package/fru-tools: Update to latest Master
  > board/analogdevicesinc/common: Add QuadMxFE FRU files
  > package: ad936x_ref_cal: ad936x_ref_cal.hash: Adjust hash
  > Merge tag '2021.02.7' of https://github.com/buildroot/buildroot.git
  > Revert "Update for 2020.02.8"
  > package: libm2k: Bump to Version 0.5.0

Submodule u-boot-xlnx a2c2013..90401ce:
  > include/configs/zynq-common: Pluto forward compatibility dt node /axi

Submodule linux fe8b7e5..9dfba10:
  > arch: arm: boot: dts: zed+ad4630: update hdl tag
  > dts: vcu118_ad9081.dts: Add axi-data-offload engine support
  > dts: vcu128_ad9081.dts: Fix axi-data-offload node names
  > iio: jesd204: xilinx_transceiver.c: Fix error handling
  > drivers: iio: addac: one-bit-adc-dac: Remove unused var
  > drivers: iio: addac: one-bit-adc-dac: Fix read_label()
  > arch: arm: boot: dts: Add ad4630-24 dts
  > drivers: iio: adc: AD4630
  > Documentation: ABI: testing: Add ad4630 sysfs description
  > dt-bindings: iio: adc: Add docs for ad4630
  > drivers: pwm: axi-pwmgen: Add PWM ops
  > Documentation: ABI: testing: pwm: Add time_unit
  > drivers: pwm: axi-pwmgen: Add time unit support
  > Documentation: driver-api: pwm.rst: Add time_unit
  > drivers: pwm: core: Add PWM time unit
  > include: linux: pwm.h: Fix pwm_apply_args
  > Documentation: pwm: Add phase documentation
  > drivers: pwm: sysfs: Add phase sysfs
  > include: linux: pwm: Convert phase to u64
  > pwm: Convert period and duty cycle to u64
  > drivers: pwm: axi-pwmgen: Rename offset
  > include: linux: pwm.h: Rename offset
  > drivers: usb: chipidea: Let the PHY set VBUS
  > arch: arm: boot: dts: Remove unused usb-phy
  > arch: arm : boot: dts: set vcxo to 100 MHz
  > arch: arm: dts: de10nano: add sysid support
  > zynqmp-zcu102-rev10-ad9082: fix HDL project tag
  > arch: arm: boot: dts: rename SPI Engine AXI CLKGEN
  > arch: arm: dts: add socfpga_arria10_socdk_adrv9002 dts
  > arch: arm64: xmicrowave.dts: enable detector
  > arch: arm64: xmicrowave.dts: add labels
  > net: adi: adin1110: Fix multicast filter
  > net: adi: adin1110: Set frames as forwarded
  > net: ethernet: adi: adin1110: Add unicast ability flag
  > arch: arm: dts: zynq-zed-otg.dts Add fpga-axi dt node
  > arch: arm64: dts: zcu102-cn0506: add sysid support
  > net: ethernet: adi: adin1110: Fix forwarding
  > net: ethernet: adi: adin1110: Fix MAC address masking
  > dts: xilinx/adi-ad9083-vna: Updates for board Rev.B
  > iio: frequency: adf4371: Support for RFAUX8 VCO output mux
  > iio: frequency: ad9528: jesd204-fsm ignore SYSREF rate issues in SC0
  > dt-bindings: net: adin2111: Add docs
  > net: ethernet: adi: adin1110: Add adin2111 support
  > net: ethernet: adi: adin1110: Fix mutex unlock path
  > net: phy: adin1100: Add ADIN2111 PHY_ID
  > net: ethernet: adi: adin1110: Fix TX space read
  > microblaze: configs: adi_mb_defconfig: Add IPv6 support and sync options
  > iio: beamformer: adar1000: Make gain write/read consistent
  > arch: arm: sockit_arradio: Remove vip-frame-reader
  > bindings: clock: ad9545: fix zero delay property
  > clk: ad9545: fix zero delay property
  > iio: adc: talise: Update to Talise API version: 3.6.2.1
  > firmware: Talise[TDD|Rx|Tx]ArmFirmware: Update to ARM Revision: 6.2.1
  > iio/jesd204/axi_jesd204_[rx|tx]: link running increase retry count
  > jesd204: jesd204-fsm: FSM messages include topology_id
  > iio: jesd204: axi_jesd204_[rx|tx].c: Fix uninit for optional clocks
  > jesd204: jesd204-fsm: Fix paused/resume notice messages
  > dts: zynqmp-zcu102-rev10-ad9082-204c-txmode22-rxmode23-dual: Remove node
  > ci: fix build inside docker
  > iio: multiplexer: iio-gen-mux: Fix potential NULL pointer access
  > microblaze: configs: adi_mb_defconfig: Add IIO generic MUX support
  > iio: adc: ad9361: Fix type for split_gain_table_abs_gain
  > dts: zynqmp-zcu102-rev10-ad9081-m8-l4-ffh: Use gpio-muxes for FFH
  > dts/vcu118_quad_ad9081_204b_txmode_9_rxmode_10: Add Rx/Tx FFH support
  > dts: vcu118_quad_ad9081.dtsi: Let the driver control GPIO_0 HDL mux mode
  > iio: adc: ad9081: GPIO_X resource sharing between NCO sync and DAC FFH
  > iio: adc: ad9081: Add attribute to control RX FFH GPIO mode
  > iio: adc: ad9081: Move sync pin configuration after setup_[rx|tx]
  > arch: arm64: dts: zcu102-fmcomms8: add sysid support
  > Kconfig.adi: select ADIN1110 for build
  > dt-bindings: net: adin1110: Add docs
  > net: adi: adin1110: Add initial support
  > net: phy: adin1100: Add ADIN1110 PHY_ID
  > arch: arm: dts: zynq-coraz7s: add sysid support
  > ci: fix building inside docker
  > iio:accel:adxl313: Move exports into IIO_ADXL313 namespace
  > dt-bindings: iio: accel: Add binding documentation for ADXL313
  > iio: accel: Add driver support for ADXL313
  > arm: configs: zynq_xcomm_adv7511_defconfig: Update using savedefconfig
  > arch: arm64: dts: change jesd subclass for zynqmp-zcu102-rev10-ad9695
  > arch: arm: zynq_xcomm_adv7511_defconfig: Enable dt/FPGA overlay support
  > dts: vcu118_quad_ad9081_204b_txmode_5_rxmode_6: New M4, L2 8B10B mode
  > arch: arm: dts: add zed dts for eval adf4377
  > drivers: iio: Kconfig.adi: add ADF4377
  > iio: frequency: adf4377: Add sysfs ABI doc
  > iio: frequency: add support for adf4377
  > dt-bindings: iio: frequency: add ADF4377 doc
  > arch: arm: dts: Add devicetree for EVAL-AD9783
  > drivers: iio: adc: Add support for AD9783
  > Documentation: bindings: Add docs for AD978X
  > arch: arm64: adi_versal_defconfig: Extend Kuiper support
  > arch: arm64: adi_zynqmp_defconfig: Extend Kuiper support
  > arch: arm: zynq_xcomm_adv7511_defconfig: Extend Kuiper support
  > arch: arm: socfpga_adi_defconfig: Extend Kuiper support
  > iio:imu:adis16480: fix buffering for devices with no burst mode
  > arch: arm: dts: Add zedboard with otg enabled
  > clk: clk-ad9545: move to 'devm_of_clk_add_hw_provider()'
  > clk: clk-ad9545: get dpll profile properties in separate function
  > clk: clk-ad9545: handle first optional dt properties
  > iio: hmc7044: add error checking for 'devm_add_action_or_reset()'
  > jesd204: core: fix dts overlay handling
  > clk: clk-conf: properly release of nodes
  > clk: clk-ad9545: properly release fwnode handles
  > clk: clk-ad9545: don't use child node's to identify the 'pll-clk' node
  > clk: clk-ad9545: fix 'adi,fast-acq-trigger-mode' reading
  > clk: clk-ad9545: make sure to remove the clk provider
  > configs: zynq_xcomm_adv7511_defconfig: Enable NFS support
  > iio: adc: ad9081: Support for AD9177, AD9207 & AD9209 chip variants
  > arm64: dt: zynqmp-zcu102-rev10-ad9081-m8-l4-ffh: FFH test support
  > arm64: dt: adi-ad9081-fmc-ebz: Prefer external reference if available
  > iio: adc: ad9081: Option to select the GPIO used for MS NCO sync
  > dt-bindings: adi,ad9081.h: Add FFH GPIO defines
  > iio: adc: ad9081: Fast Frequency Hopping support
  > iio: Kconfig.adi: select LTC2688
  > dt-bindings: iio: Add ltc2688 documentation
  > iio: ABI: add ABI file for the LTC2688 DAC
  > iio: dac: add support for ltc2688
  > iio: frequency: ad9528: jesd204-fsm add clock synchronization state
  > arch: arm64: dts: add zynqmp-zcu102-rev10-ad9695 dts
  > iio: adc: ad9208: Fix ad9695
  > arch: arm64: dts: stingray: Make vcxo100/122.88 distinction
  > arch: dts: zynq-zed-adv7511-cn0363: disable EEPROM
  > arch: arm: dts: zynq-zed-adv7511: disable EEPROM
  > arch: arm: dts: zed-adv7511 add eeprom label
  > arch: arm: socfpga_adi_defconfig: Enable DEBUG_FS
  > arch: arm64: dts: stingray: Enable direct clocking
  > arch: arm64: dts: stingray: Enable autorevertive reference switching
  > arch: arm64: dts: stingray: Set HMC7044 EXT_REF to 100 MHz
  > arch: arm64: dts: stingray: Move adf4371 to axi_spi_fmc
  > iio: jesd204: axi_adxcvr: Use devm_clk_get_optional() for conv2
  > iio: jesd204: axi_jesd204_[rx|tx]: Use devm_clk_get_optional()
  > CI:add echo to check builds
  > CI:fix rpi build conditions
  > CI: change artifacts structure
  > CI: sync master with rpi-5.10.y
  > dts: hmc7044: Remove adi,control0-rb4-enable;
  > iio: frequency: hmc7044: REG_CH_OUT_CRTL_0 always set reserved bit4
  > Kconfig.adi: select ADXL367 SPI & I2C
  > iio: accel: adxl367: Fix handled initialization in adxl367_irq_handler()
  > iio: accel: adxl367: unlock on error in adxl367_buffer_predisable()
  > iio: accel: add ADXL367 driver
  > dt-bindings: iio: accel: add ADXL367
  > iio: ABI: add note about configuring other attributes during buffer capture
  > iio: ABI: document mag_referenced
  > iio: introduce mag_referenced
  > arch:arm:dts:fmclidar1: update slave address
  > arch:arm:dts:ad6676: remove extra i2c node
  > arch:arm:dts:fmcadc2: remove extra i2c node
  > iio: adrv9002: make use of 'device_create_bin_file()'
  > ci: install dependencies for 'build_checkpatch()'
  > ci: improve sync_branches_with_main handling
  > ci: remove $method variable from sync_jobs
  > ci: detach xcomm_zynq merge from syncing other branches
  > jesd204: jesd204_top_device: Add jesd204-fsm user controls
  > dts: zynqmp-zcu102-rev10-ad9082...dual-multi-top.dts: Add FSM STOP states
  > dts: zynqmp-zcu102-rev10-ad9082..dual-multi-top.dts: Remove nodes
  > uio: uio_dmem_genirq: Fix NULL pointer deference
  > iio: adc: ad9371: Fix profile loading for clkPllVcoDiv=1.5
  > iio: adc: ad7124: fix mask used for setting AIN_BUFP & AIN_BUFM bits
  > arch: arm{64}: config: add adrv9002 compensated gain table
  > iio: adrv9002: support RX compensated gain tables
  > firmware: add adrv9002 compensated gain table
  > arch: arm64: dts: adi-adar3002-longs-peak.dts: Configure ADMV4420
  > iio:frequency:admv4420.c: Add support for ADMV4420
  > dt:bindings:iio:frequency: Add ADMV4420 doc
  > units: Add SI metric prefix definitions
  > iio: adc: ad9371: Additional calibrations for LO change procedure
  > iio: adrv9002: adapt to the new API
  > iio: adrv9002: api: add api to get gpio direction
  > iio: adrv9002: api: fix mixed code declarations warnings
  > iio: adrv9002: api: fix -Wframe-larger-than= for arm builds
  > firmware: Update firmware for adrv9002
  > io: adrv9002: Update API to 48.49.2
  > arch: arm64: dts: stingray: Add ZUD1A-BREAKOUT eval board EEPROM
  > iio: adc: ad9081: Only WARN in case SPI ID doesn't match chip ID
  > arch:arm:boot:dts:adrv9002: update TX DMA interrupt
  > iio: beamformer: adar1000: Fix 'phase' out of range setting
  > iio: beamformer: adar1000: Fix detector_en value
  > iio: addac: ad74413r: Do not reference negative array offsets
  > iio: addac: ad74413r: for_each_set_bit_from -> for_each_set_bit
  > iio: addac: ad74413r: correct comparator gpio getters mask usage
  > iio: addac: ad74413r: use ngpio size when iterating over mask

Submodule hdl 43cdc62...d09fc92:
  > util_do_ram: Fix Rx path for interrupted transfers
  > util_axis_fifo_asym: Fixes for simulation
  > data_offload: Fix Tx bypass
  > sysid: Add sysid support for de10nano
  > ad9083_evb_bd: Connect util_ad9083_rx_cpack reset to adc_rst
  > ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy - Added an utility buffer in order to generate the 50Mhz DRP clock. - 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.
  > vcu118: Increase Microblaze performance and clock frequency Increased the Microblaze performance for the VCU118 carrier: - Increased the size of Instruction Cache and Data Cache to 64kB
  > ad9081_fmca_ebz/a10soc: Make second sync CMOS and GPIO controllable
  > ad9081_fmca_ebz/vck190: Make second sync CMOS and GPIO controllable
  > ad9081_fmca_ebz/vcu128: Make second sync CMOS and GPIO controllable
  > ad9081_fmca_ebz/zc706: Make second sync CMOS and GPIO controllable
  > ad_fmclidar1_ebz:a10soc Fixed SPI communication on Arria 10 (#947)
  > .gitignore: Add the bd.tcl files from built IPs into gitignore
  > cn0577: Initial commit
  > axi_ltc2387: Intial commit
  > mark axi_gpreg.v as systemverilog, otherwise it gives an error with vivado 2022.1
  > ad9213_dual_ebz: Add possibility to change order of channels through a GPIO
  > ad9213_dual_ebz: Fix constraints
  > ad9083_evb_bd: make the project more generic
  > docs: Add HDL coding guideline
  > ad_quadmxfe1_ebz: Refactor MxFE GPIOs
  > ad9081_fmca_ebz/zcu102: Make second sync CMOS and GPIO controllable
  > cn0561_zed: Initial commit
  > cn0561_coraz7s: Initial commit
  > vcu128: Increase Microblaze performance and clock frequency
  > axi_dmac: Add parameter controlling AWCACHE
  > scripts/adi_board.tcl: Support connecting HPCx
  > data_offload_constr.ttcl: Fix false_paths for i_sync_src_transfer_length registers
  > ad_quadmxfe1_ebz_bd: Bugfix for JESD configurations with less lanes
  > projects/scripts/adi_board: Add support for sparse channel maping
  > library/axi_dmac: Add the BYTES_PER_BURST_WIDTH interface parameter in INTERFACE_DESCRIPTION
  > Adaq8092 on ZedBoard LVDS output mode  (#921)
  > Makefile: Replace util_fifo2axi_bridge with util_hbm
  > util_fifo2axi_bridge: Deprecate module, replaced by util_hbm
  > daq2: Do not set AXI address width for DO
  > daq2/zc706: Update to new DO storage
  > ad9081_fmca_ebz:vcu128: Disable offload bypass
  > ad9081_fmca_ebz/vcu128: Use HBM for data offload cores
  > ad9081_fmca_ebz/common: Make data offload memory type selectable
  > common/vcu128: Add HBM clocking support 450MHz
  > data_offload: Refactor core
  > util_do_ram: Initial version
  > interfaces: Data offload control interface
  > util_hbm: Initial version
  > ad9695: Add reference design for ad9695 eval board
  > arradio_c5soc: axi_hdmi_tx as framereader (#920)
  > common: Add xilinx ila utils
  > projects: ad9081: Disable tdd_sync CDC sync of TDD controller
  > library: axi_tdd: Make synchronization stage optional
  > axi_tdd: Add false paths to tdd sync input
  > library/axi_ad9361/intel: Update I/O format
  > library/data_offload: Remove empty module data_offload_control
  > library: Remove unused IPs
  > cn0506_rgmii:a10soc: Remove project as the rgmii adapter is not compatible with a10soc
  > axi_clock_monitor: Fix various issues
  > library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer
  > libraries: Correct module name according to the filename
  > adrv9009zu11eg: Added additional GPIOs and CS to the GPIO expander
  > cn0506_mii/rgmii on a10soc: update to Quartus 21.2
  > ad4630: Fix Readme
  > axi_hdmi_tx update for: ZedBoard, ZC706, ZC702, de10nano, ADRV9361-Z7035 (#897)
  > xilinx/common:ad_data_out.v: Fix typo
  > library: Adding axi_clock_monitor ip core
  > Add small check to make sure readme.md files are in projects
  > ad9083: Add reference design for ad9083_a10soc
  > xilinx/common: Add CLKEDGE parameter to ad_data_* module
  > ad9208_dual_ebz: Update Board Product Page link
  > account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
  > sidekiqz2: Updated Readme to link the ADALM-Pluto documentation
  > ad_quadmxfe1_ebz_bd: Connecting all the unused lanes in util_xcvr
  > projects/scripts/adi_board.tcl: Fix padding error caused by lane_map in ad_xcvrcon procedure
  > util_mii_to_rmii: Fix 100 Mbps configuration functionality
  > pluto_ng: Add Readme.md file
  > adrv2crr_fmcxmwbr1: Initial commit
  > add ability to customize Xilinx IP library version to value other than "user" from a global variable.
  > ad9083: Using variables instead of hard coded nets
  > ad9081_fmca_ebz: Update parameter description
  > ad9082_fmca_ebz: Update parameter description
  > ad_quadmxfe1_ebz: Update parameter description
  > axi_adrv9001: Expose IODELAY_CTRL parameter to top level
  > adrv9001_zed: Fix irq overlap
  > vcu128/vcu128_system_constr: Enable internal diff term for Ethernet clock
  > vcu118/vcu118_system_constr: Enable internal diff term for Ethernet clock
  > ad_ip_jesd204_tpl_adc: Fix latency of valid signal
  > adrv9009/zcu102: Hook up ref clock from IBUFDS_GT
  > adrv9009/zc706: Hook up ref clock from IBUFDS_GT
  > adrv9009/common/adrv9009_bd: Take ref clock from the IBUFDS_GT
  > adrv9371x/kcu105: Hook up un-gated ref clock to fabric
  > adrv9371x/zcu102: Hook up un-gated ref clock to fabric
  > adrv9371x/zc706: Hook up un-gated ref clock to fabric
  > adrv9371x: Use the output of IBUFDS_GTE2 as reference for the clock gens
  > projects/scripts: Add gtwizard scripts
  > Revert "intel: Update projects to use ad_iobuf instead of ALT_IOBUF"
  > dac_fmc_ebz: NUM_LINKS added to system_top.v
  > ad_quadmxfe1_ebz: Fix external sync for ADC path
  > dac_fmc_ebz_vcu118: Initial commit
  > dac_fmc_ebz_bd.tcl: Updated bd for multiple tx_ref_clk
  > ad9081_fmca_ebz/common: Connect sync at TPL level
  > adrv9009zu11eg: Drive cpack/upack reset from TPL
  > adrv9009zu11eg/common: EXT_SYNC updates
  > ad_ip_jesd204_tpl_ : Add missing dependency
  > ad_ip_jesd204_tpl_adc: Refactor external sync
  > common/up_adc_common: Add ext sync regs
  > common/up_dac_common: Add manual sync request
  > common/up_dac_common: Add support for explicit disarm control
  > jesd204/ad_ip_jesd204_tpl_dac: External sync refactor
  > common/up_xfer_cntrl: Fix transfer done timing
  > ad7134_fmc: Update Readme
  > ad7134_fmc: Switch offload trigger to falling ODR
  > ad7134_fmc: Change ODR signal to output
  > projects/cn0506_rmii/*: Add util_mii_to_rmii library to project
  > util_mii_to_rmii: Initial commit
  > pluto_ng: Initial commit
  > de10nano: changed quartus version to 20.1.1
  > ad_dds: Fix DDS start samples
  > ad77681evb: Fix irq overlap
  > daq3: Parameterize JESD204 configuration values
  > ad6676evb: Parameterize JESD204 configuration values
  > ad6676evb: Update to JESD204 TPL instantiation
  > ad9783: Clean-up parameters and module instances
  > ad9783: Add Readme.md
  > axi_ad9361: make IODELAYCTRL insertion optional
  > axi_dmac: Hook up ID
  > daq2: Parameterize JESD204 configuration values
  > ad9783: Update Makefile
  > adrv9009: Parameterize JESD204 configuration values
  > scripts/adi_xilinx_device_info_enc.tcl: Change regex for vcu128
  > adrv9371x: Parameterize JESD204 configuration values
  > projects/scripts/adi_board/tcl: Updated ad_xcvrcon procedure for parametrized projects
  > library/jesd204/jesd204_common/pipeline_stage.v: Initialize pipeline stage register
  > adrc9361_ccfmc: Fix SFP pin locations
  > fmcjesdadc1: Parameterize JESD204 configuration values
  > library/jesd204: tpl timing bug fix
  > ad9783_zcu102_dev: Initial commit
  > axi_ad9783: Initial commit
  > util_pulse_gen: Reload registers when counter is at one
  > adrv9009zu11eg/adrv2crr_xmicrowave: Update Makefile
  > xmicrowave: Fix typo
  > axi_adrv9001: Add external sync support
  > projects: set Quartus version for cyclone5, cn0506_mii and cn0506_rgmii
  > fmcadc2: Parameterize JESD204 configuration values
  > fmcadc2: Update JESD204 TPL instance
  > axi_adrv9001/axi_adrv9001_core.v: Disable TDD and IOCTRL if second SSI interface is disabled
  > axi_adrv9001/axi_adrv9001_tdd.v: Add disable option for TDD
  > axi_adrv9001: Hide disabled interfaces
  > axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional
  > ad9081_fmca_ebz: Fix signal length parameter
  > README.md: Add link to boot partition files download link
  > fmcjesdadc1: bd: Clean trailing white spaces and alignment
  > fmcjesdadc1: bd: Replace hardcoded lane number with parameter
  > ad9081_fmca_ebz: versal: Remove unused GT reset input pin
  > ad9081_fmca_ebz/vcu128: Remove ref clock replica
  > axi_ad7616: Fix sync port
  > ad7616_sdz: Add make env argument for interface
  > pulsar_adc_pmdz: Initial commit
  > zcu102: ad_fmclidar1_ebz, fmcomms5, fmcomms8 (#811)
  > jesd204_rx/jesd204_lane_latency_monitor.v: Fix for datapath width of 4
  > scripts/adi_board.tcl: improvements for vcu128 DDR controller
  > ad9081_fmca_ebz:vcu128: Initial version
  > projects/common/vcu128: Initial VCU128 support
  > ad9081_fmca_ebz: versal: Remove external gt_reset logic
  > ad9081_fmca_ebz: versal: Rename nets
  > ad9081_fmca_ebz/common/versal_transceiver.tcl: Reset also PLL
  > ad9081_fmca_ebz/vck190: Updated to hierarchical versal transceiver
  > jesd204_versal_gt_adapter_rx/tx: Infer Versal GT interface
  > ad9081_fmca_ebz/vck190: Change default profile to 2 lanes
  > ad463x: Fix readme
  > ad9213_dual_ebz: Readme.md : Remove incorrect product page
  > ad9082_fmca_ebz: Readme.md:  Remove AD9081 from parts
  > ad9208_dual_ebz: Readme.md: Remove invalid product page
  > axi_adrv9001/intel: Add dummy parameters to match Xilinx interface
  >  ad_quadmxfe1_ebz : Add readme file
  > ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters
  > adrv9009zu11eg/adrv2crr_fmcomms8: Add clock buffers for core clocks
  > ad_quadmxfe1_ebz: Initial version
  > library:util_pad: Initial version
  > jesd204/scripts: Helper procedure for TPL width calculation
  > axi_dmac: Allow wider FIFO/AXI Stream interface
  > start adding some doc to the ./projects directory
  > projects: fixed xcvr clocks that generated critical warning
  > adrv9001/zed: Use global clock buffers for better fit the design
  > axi_adrv9001: Add the option of global clock buffers on 7 series
  > library/scripts/adi_xilinx_device_info_enc.tcl: Add K26 support
  > axi_i2s_adi: initialize cdc_sync_stage0_tick bits to '0'
  > axi_hdmi_tx: Add UltraScale+ architecture to Verilog
  > fmcjesdadc1: Fix ad9250 core parameters settings
  > ad_ip_jesd204_tpl_adc: Add value of 14 to CONVERTER_RESOLUTION parameter
  > generate_xml.sh: Replace <  and > in error message
  > xmicrowave: Initial commit
  > vc709_carrier: Add vc709 carrier (#788)
  > ad_ip_jesd204_tpl_dac: Move external dac sync bit
  > library/common/up_adc_common.v: Remove tabs
  > library/common/up_dac_common.v: Cleanup spaces
  > adxcvr: Increase version to 17.5.a
  > adrv9001/zcu102: Enable independent TX mode in CMOS
  > axi_adrv9001/adrv9001_rx.v: Simplify clocking
  > projects/adrv9001/zcu102/lvds_constr.xdc: Fix timing constraints
  > data_offload: Fix oversized TX input transactions
  > Revert "data_offload: Fix oversized inputs in TX mode"
  > projects: remove hardcoded div_clk from xcvr
  > ad463x_data_capture: Remove tb
  > ad463x: Fix readme
  > library: Add link to wiki for IPs
  > ad4630_fmc: Initial commit
  > ad463x_data_capture: Initial commit
  > spi_engine_execution: Delete control loop-back in  sdi_data_valid generation
  > axi_spi_engine: Add generic config params
  > spi_engine/data_reorder: Initial commit
  > library/tb: Improve run_tb.sh
  > daq2/zcu102: Fix the ad9144 data offload to use internal BRAM
  > daq2/kcu105: Fix the ad9144 data offload to use internal BRAM
  > daq2/kc705: Fix the ad9144 data offload to use internal bram
  > daq2/zc706: Increase BRAM utilization to 52%
  > scripts: Add logic for vivado version check
  > Revert "data_offload: Fix timing violation"
  > scripts/adi_board.tcl: For older families stick with axi_interconnect
  > jesd204_rx: fixed makefile
  > jesd204/ad_ip_jesd204_tpl : Add support for 12 lanes
  > projects/ad9081_fmca_ebz: Updated makefiles
  > Makefile: Fix misc makefiles from projects and library
  > jesd204/jesd204_rx: Define tie off values for unused ports
  > jesd204/jesd204_tx/jesd204_tx.v: Have FFs initial value, useful for simulation
  > ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock
  > ad9081_fmca_ebz/common: Drive Rx DMA system side with DMA clock
  > ad9081_fmca_ebz/vck190: Initial version
  > ad9081_fmca_ebz/common: Add Versal transceiver support
  > jesd204:jesd204_versal_gt_adapter_rx/tx: Add adapter for Versal transceiver IP
  > common/vck190: Initial version
  > common/vmk180_es1: Initial version
  > common/vmk180: Initial version
  > scripts/adi_project_xilinx.tcl: VCK190 support
  > scripts/adi_project_xilinx.tcl: Install ES1 board from XHUB, make project compile in batch mode
  > scripts/adi_project_xilinx.tcl: Add VMK180 & VMK180_ES1 support
  > scripts/adi_board.tcl: Versal support for memory interconnect and irq interconnect
  > scripts/adi_xilinx_device_info_enc.tcl: Add Versal support
  > scripts/adi_ip_xilinx.tcl: Enable auto family support
  > scripts/adi_board.tcl: Switch cpu_interconnect to SmartConnect
  > scripts/project-xilinx.mk: Update target to xsa and cleanup list
  > .gitignore: Ignore Versal files
  > Update README.md
  > scripts: QUARTUS_VERSION and PRO_ISUSED can be set in system_project.tcl
  > s10soc: Update base desgin from ES to production, H-Tile version
  > ad9213_dual_ebz: Initial commit
  > s10soc:ad_cpu_interconnect: Add an avl_address_width attribute
  > data_offload: Fix util_[cu]pack offset to TDD syncs
  > ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design
  > adi_project_intel.tcl: update quartus to 21.2
  > data_offload: Fix oversized inputs in TX mode
  > axi_adxcvr_ip.tcl util_adxcvr_ip.tcl: Fixed asynchronous resets critical warnings in XCVR
  > adi_project_xilinx.tcl, adi_ip_xilinx.tcl: update version to 2021.1
  > data_offload: Fix timing violation
  > data_offload: Add sync to cyclic mode
  > axi_pwm_gen: Add config in soft reset option
  > Makefiles: Update header with the appropriate license
  > Make system: Be explicit in license that cover the make/build system
  > JESD204 Interface Framework : add logo
  > HDL Logo: Add
  > ad_mem_asym: Add option to control cascade layout
  > scripts: Add *.gen to clean list
  > spi_engine_execution: Fix cs signal generation
  > fmcjesdadc1: Update block design (#743)
  > util_tdd_sync: Narrow scope of false path to D pin
  > data_offload: Improve external synchronization
  > axi_adxcvr:util_adxcvr: Correctly defined resets.
  > adrv9001[intel]: Add second pair of DMAs
  > ad400xx_fmc: Parametrize board select, sampling rate and adc resolution
  > adrv9009zu11eg & common/zcu102 : Fix zynqmp ref clock definition
  > daq2: Connected loose ad9144 dunf flag that fixes the critical warning
  > Revert "adrv9009zu11eg: Integrate data_offload"
  > axi_adrv9001: Add support for symbol operation mode on Xilinx devices
  > jesd204/ad_ip_jesd204_tpl_dac: Intel: Add support for AD916x preset files
  > Update Quartus version to 20.4
  > adi_make: Update bin build flow for 2020.1 tools
  > data_offload: Fix support for > 4 GiB of storage
  > data_offload: Fix MEM_SIZE parameter width
  > data_offload: Fix m_axis output stability issue
  > data_offload: Fix duplicated output samples
  > data_offload: Fix data_offload getting stuck on oscillating m_saxis_ready
  > data_offload: Fix oneshot mode
  > data_offload: write_fsm: Always transition out of idle on high init_req
  > data_offload: Bump hdl version
  > data_offload: Fix AXI register map
  > ad9081_fmca_ebz: Remove bypass gpio
  > data_offload: Fix readme images
  > ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine
  > data_offload: Update README and generic block design
  > data_offload: Add block diagrams
  > data_offload: Flush the DMA if the transaction size is bigger than the storage
  > data_offload: Calculate AXI_ADDRESS_LIMIT automatically
  > data_offload: Delete fifo_dst_rlast
  > daq2/zc706: PL DDR size is 1GByte
  > data_offload_bd: Calculate the address limit from the address width
  > data_offload: Fix alignment of write last beat and write full
  > data_offload: Improve timing in regmap
  > data_offload: Fix fifo_dst_ready generation
  > adrv9009zu11eg: Integrate data_offload
  > daq2: Integrate data_offload
  > data_offload: Add integration process for Xilinx carriers
  > data_offload: Initial commit
  > ad_axis_inf_rx: Initialize output ports to avoid X propagation in simulation
  > interfaces: Add XFER_REQ to fifo_rd_rtl.xml
  < pluto: Fix dunf connection
  > pluto: Fix dunf connection
  > util_fifo2axi_bridge: Initial commit
  > util_axis_fifo_asym: Initial commit
  > axi_generic_adc: pass in number of channels instantiated to up_adc_common. Allows drivers/iio/adc/ad_adc.c driver to be used with this core.
  > adi_project_xilinx.tcl: Set default value of ADI_USE_OOC_SYNTHESIS to 1
  > Update Vivado version to 2020.2
  > ad9083: Removed FIFO and increased DMAC transfer length
  > Fix width of device_cfg_octets_per_multiframe
  > jesd204/ad_ip_jesd204_tpl_dac: Support for F=64
  > jesd20r_rx/jesd204_tx: Support for F=64
  > esd204/ad_ip_jesd204_tpl_adc: Support more datapath widths
  > ad_ip_jesd204_tpl_adc: Max number of lanes is 32
  > adi_jesd204: Add support of 16 lanes
  > adrv9371x: remove IOB attribute from rx and rx_os
  > adi_board: Fix ad_connect command tracing
  > ad_fmclidar1_ebz: Remove invalid ad_connect invocations
  > axi_pwm_gen: Fix offset mechanism
  > scripts/adi_project_xilinx: Set number of parallel OOC jobs through environment variable
  > tb: jesd204: update and automate frame_align_tb
  > adi_board: Rewrite ad_connect to support all input permutations
  > adrv9001: fixes for reset metastability on xilinx ioserdes
  > axi_dmac: Restore axi_dmac_regmap_request to f7b8a2d version
  > axi_tdd: Add standalone axi_tdd IP core
  > xilinx/axi_adxcvr/axi_adxcvr_mdrp: Fix read if all channels are selected
  > Revert "modified transceiver configuration files"
  > adrv9001:a10soc:system_qsys.tcl: set clock polarity to 0
  > up_tdd_cntrl: Add magic value "TDDC"
  > axi_ad9361: Fix typo in tdd interface
  > axi_adxcvr: Increase version to 17.4.a
  > xilinx/axi_adxcvr: Expose PLL status in status bit
  > util_adxcvr: Hook up RXPROGDIVRESET
  > ad9081_fmca_ebz/zcu102: Enable 204C modes
  > scripts/adi_board.tcl: Use div2 out clock from xcvr in case of GTH and 204C
  > util_adxcvr: Add 204C support for GTH3/4
  > util_adxcvr/util_adxcvr_xch: Place 204C logic to a common place
  > ad9081_fmca_ebz/zcu102: Fix spaces
  > ad469x: Clean system_project.tcl
  > Fix registers mismatches in regmap_tb from jesd 204 rx/tx and dmac
  > axi_adrv9001: Let gate signals have initial value, useful for simulation
  > axi_adrv9001: rx: calculate ramp value based on received value
  > axi_adrv9001:rx: Add reset to link layer
  > axi_adrv9001:rx:phy: do not generate valid while in reset
  > axi_adrv9001: Allow running Rx2/Tx2 channels in R1 mode without Rx1/Tx1
  > common/up_dac_common: Expose r1_mode in up clock domain to prevent deadlock
  > adrv9001/zcu102: Enable independent Tx from Rx in CMOS mode
  > axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks
  > adrv9001/a10soc: Initial version
  > Correct constraints file pin mapping
  < adrv9001/zcu102: Enable independent TX mode in CMOS
  < axi_adrv9001: Allow running Rx2/Tx2 channels in R1 mode without Rx1/Tx1
  < common/up_dac_common: Expose r1_mode in up clock domain to prevent deadlock
  > ad9081_fmca_ebz/zcu102: Differentiate parameters based on lane rate
  > ad9081_fmca_ebz/zcu102: Fix typo
  > ad9081_fmca_ebz: Fix for F=8
  > util_adxcvr/util_adxcvr_xch: Fix typo
  > ad9081_fmca_ebz/vcu118: Adjust QPLL params and diff swing
  > util_adxcvr: GTY TX phase and delay alignment circuit power down.
  > util_adxcvr: Add PPF1_CFG parameter
  > ad9082_fmca_ebz: Use 9081 system_bd, updated comments
  > ad9081_fmca_ebz: Update path to common block design
  > ad9081_fmca_ebz: Add LANE_RATE param to all projects
  > ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link
  > ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR
  > ad9081_fmca_ebz: Disable XBAR from DAC TPL
  > util_adxcvr: Add LANE_RATE parameter so it can be used for automatic constraint generation
  > xilinx/util_adxcvr: 204C link support for GTY4
  > xilinx/axi_adxcvr: Add 204C support, increase version to 17.3.a
  > scripts/adi_board.tcl: In 204C do not connect SYNC
  > jesd204/jesd204_common/sync_header_align: Initial version
  > jesd204/axi_jesd204: Complete clock definitions in out of context mode
  > jesd204: Add out of context constraint file for link layer cores
  > axi_pulse_gen: Fix typo introduced in c235e5e58
  > Testbenches: Unify and optimize HDL testbenches
  > axi_pwm_gen: Initial commit
  > ad9083_evb: Update parameters to 10Gpbs lane rate
  > sysid: Make sure gitbranch_string is always declared
  > ad469x/zed: Add multicycle path constraint
  > jesd204_rx_constr.ttcl: Remove ASYNC_REG constraint from i_lmfc/cdc_sync_stage1_reg
  > xilinx/axi_adxcvr: Increase version to 17.02.a to show PRBS capability
  > xilinx/axi_adxcvr/axi_adxcvr_up: Fix force error control bit
  > adrv2crr_fmcomms8: Fix system_top.v
  > axi_spi_engine: almost full and almost empty is generated by the util_axis_fifo
  > axi_spi_engine: Fix IRQ generation
  > axi_spi_engine: Fix level/room width for the CDC FIFOs
  > axi_adrv9001: Add status bit for Tx clocking
  > util_axis_fifo: Improve GUI layout in Vivado
  > adrv9009zu11eg_crr: Update spi
  > ad9083: Add reference design for ad9083 eval board
  > adrv9001/zc706: Fix spaces
  > adrv9001/zc706: Fix comments HPC to LPC
  > util_axis_fifo: Add REMOVE_NULL_BEAT_EN feature
  > util_axis_fifo: Add TKEEP support
  > util_axis_fifo: Fix FIFO is full alignment
  > util_axis_fifo: Switch data and tlast order, improve maintainability
  > Update Quartus Prime version from 19.3.0 to 20.1.0
  > jesd204/ad_ip_jesd204_tpl_dac: Drop LSBs from wider bus to be compatible with previous implementations
  > jesd204_rx: Set ASYNC_REG attribute for double syncs
  > jesd204_rx:jesd204_rx_ctrl_64b: Improve timing closure
  > jesd204/jesd204_rx: Make output pipeline stages opt in feature
  > jesd204/ad_ip_jesd204_tpl_adc: Make frame alignment opt-in feature
  > jesd204_tx:64b: Remove reset
  > jesd204_rx:64b: Remove reset
  > ad_ip_jesd204_tpl_dac: fix capability reg
  > ad9082_fmca_ebz:zc706: Initial version
  > ad9082_fmca_ebz:zcu102: Initial version
  > ad9082_fmca_ebz:vcu118: Initial version
  > ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size
  > axi_adrv9001: Double sync control lines between interface 1 and 2
  > axi_ad9361: Update constraints in case TDD is disabled
  > adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
  > fmcomms2/zed: Disable unused TDD to save space and timing
  > axi_adrv9001: Fix channel 3 for Tx1 in DMA mode
  > axi_adrv9001: Quartus 19.3 updates
  > adrv9001/zc706: Initial commit
  > axi_dmac: fix non-blocking assignment in combinatorial block
  > jesd204/jesd204_tx: Expose character replacement capability
  < axi_adrv9001: Quartus 19.3 updates
  < axi_adrv9001: Double sync control lines between interface 1 and 2
  < axi_ad9361: Update constraints in case TDD is disabled
  < adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
  > cn0540/cora: Remove multicycle constraint
  > util_axis_fifo: Add almost empty and almost full support
  > library.mk: Update CLEAN_TARGET
  < fmcomms2/zed: Disable unused TDD to save space and timing
  < axi_adrv9001: Fix channel 3 for Tx1 in DMA mode
  < axi_adrv9001: rx: calculate ramp value based on received value
  < axi_adrv9001: Let gate signals have initial value, useful for simulation
  < axi_adrv9001: Add status bit for Tx clocking
  < axi_adrv9001:rx: Add reset to link layer
  < axi_adrv9001:rx:phy: do not generate valid while in reset
  < library/common/up_tdd_cntrl: Make address generic
  < adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing
  < adrv9001/common: Run DMAs @ 100MHz
  < axi_adrv9001: Add opt-in synthesis parameters
  < axi_adrv9001: Use global clocks for divided down clock
  < ad_pnmon: Fix zero checking when valid not constant
  < axi_adrv9001:axi_adrv9001_rx_channel: fix ramp signal checking
  < ad_tdd_control: Avoid single pulses if tx_only or rx_only
  < ad_tdd_control: Fix rx/tx only behavior
  < adrv9001/zed: Connect TDD sync to PMOD JA1
  < common/up_tdd_cntrl: Fix read data when read is idle
  < adrv9001/zcu102: Add TDD sync to PMOD0 J55.1
  < adrv9001/common: Export TDD mode signal
  < axi_adrv9001: Export TDD mode
  < adrv9001/zed: Add TDD support
  < adrv9001/zcu102: Add TDD support
  < axi_adrv9001: Add TDD support
  >  scripts/adi_board.tcl: Add simulation support
  > util_axis_fifo: Add TLAST to the streaming interfaces
  > util_axis_fifo: Fix slave reset interface definition
  > ad9081_fmca_ebz/vcu118: Added common 204C use cases as example
  > ad9081_fmca_ebz: Remove system reset from Xilinx PHY
  > ad9081_fmca_ebz/a10soc: Np 12 support
  > fmcadc5: Connect link clock to second JESD link layer
  > ad_fmclidar1_ebz: Set bits per sample towards the DMA interface
  > ad9208_dual_ebz: Use ad_xcvrcon procedure to connect device clock
  > ad9081_fmca_ebz/zcu102: Add case analysis to select correct out clock frequency
  > ad9081_fmca_ebz: Np 12 support
  > jesd204: Increase Rx version to 1.07.a
  > jesd204: Increase Tx version to 1.06.a
  > jesd204: Intel: NP12 support
  > intel/common/up_clock_mon_constr: Make constraint more generic
  > jesd204/ad_ip_jesd204_tpl:Intel: NP 12 support
  > intel/jesd204_phy: Remove device clock from the interface
  > jesd204/tb: Update testbenches
  > jesd204_tx_static_config: Update to Np 12 interface changes
  > jesd204_rx_static_config: Update to Np 12 interface changes
  > jesd204: Expose core synthesis parameters through registers
  > jesd204: Xilinx: NP=12 support
  > common/ad_upack: Generic unpacker core and testbench
  > common/ad_pack: Generic packer core and testbench
  > jesd204: Make character replacement opt in feature
  > jesd204: Fixed TX frame mark timing. Added start and end of multiframe signals as RX and TX ports
  > jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement
  > adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8
  > fmcomms8: zcu102: Fix lane swapping
  > util_axis_fifo: Add support for tlast
  > ad9081_fmca_ebz: a10soc: Initial version
  > common/a10soc: Bridge support
  > common/intel: Add util_adcfifo integration script
  > ad40xx/zed: Update constraints
  > ad40xx/xilinx: Activate AXI_SLICE_SRC for the DMA
  > spi_engine_execution: Add constraints file
  > spi_engine_execution: Add echoed SCLK support
  < adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8
  < fmcomms8: zcu102: Fix lane swapping
  > util_adxcvr: Fix PRBS synchroniser typo
  > adrv9001/zcu102: Add debug header
  > adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing
  > adrv9001/common: Run DMAs @ 100MHz
  > axi_adrv9001: Add opt-in synthesis parameters
  > axi_adrv9001: Use global clocks for divided down clock
  > ad_pnmon: Fix zero checking when valid not constant
  > axi_adrv9001:axi_adrv9001_rx_channel: fix ramp signal checking
  > cn0501/coraz7s: Fix sysid
  > ad_tdd_control: Avoid single pulses if tx_only or rx_only
  > up_tdd_cntrl: Split large synchronizer in smaller ones
  > ad_tdd_control: Fix rx/tx only behavior
  > adrv9001/zed: Connect TDD sync to PMOD JA1
  > common/up_tdd_cntrl: Fix read data when read is idle
  > adrv9001/zcu102: Add TDD sync to PMOD0 J55.1
  > adrv9001/common: Export TDD mode signal
  > axi_adrv9001: Export TDD mode
  > adrv9001/zed: Add TDD support
  > adrv9001/zcu102: Add TDD support
  > axi_adrv9001: Add TDD support
  > library/common/up_tdd_cntrl: Make address generic
  > makefile: Regenerate make files
  > ad40xx: Fix bd.tcl script
  > sysid: Upgrade framework, header/ip are now at 2/1.1.a
  > ad9081:zcu102: Expose parameters to environment
  > util_axis_fifo: Add KEEP synthesis attribute for zerodeep CDC
  > usrpe31x: Use adi_project_create instead of adi_project
  > sidekiqz2: Use adi_project_create instead of adi_project
  > adrv936x: Use adi_project_create instead of adi_project
  > pluto: Use adi_project_create instead of adi_project
  > m2k: Use adi_project_create instead of adi_project
  > adrv9009zu11eg: Use adi_project_create instead of adi_project
  > adi_project_xilinx: Fix the adi_project process
  > project-xilinx.mk: Add *.hbs to clean list
  > vc707: Fix mdio intf
  > adi_project_xilinx: Add env var
  > adi_ip_xilinx: Add env var
  > adi_xilinx_msg: Downgrade Synth 8-2490
  > tcl: Change Vivado version to 2020.1
  > de10nano: Add hps_conv_usb_n signal to stabilize UART lines
  < daq3:zcu102: Connect overflow pins for the AD9680 TPL
  > fmcomms8/intel: Fix fPLL configuration
  > ad9371x/intel: Fix fPLL configuration
  > adrv9009/intel: Fix fPLL configuration
  > intel/jesd204: clock_source instance version is 19.3
  > scripts: allow directly specifying a device when creating a project
  > xilinx:adxcvr: PRBS support
  < Revert "intel: Update projects to use ad_iobuf instead of ALT_IOBUF"
  < de10nano: Add hps_conv_usb_n signal to stabilize UART lines
  > axi_spi_engine: Fix util_axis_fifo instance related issues
  < axi_hdmi_tx: Remove deprecated constraint
  < adv7513_de10nano: Fix gpio_bd assignments
  < common/de10nano: Cosmetic updates only
  < common/de10nano: Full HD 60 FPS support
  > cn0501: Initial commit for Coraz7s
  > ad7768_if: Remove buffers, add parallel data path
  > adi_jesd204: Configure fPLL phase aligned mode
  > axi_hdmi_tx: Remove deprecated constraint
  > adv7513_de10nano: Fix gpio_bd assignments
  > common/de10nano: Cosmetic updates only
  > common/de10nano: Full HD 60 FPS support
  > axi_dmac: Update IP with the new util_axis_fifo
  > spi_engine: Update util_axis_fifo instances
  > util_axis_fifo: Refactoring
  > ad_mux: another fix cases where channel number is not power of mux size
  > ad_mux: fix cases where channel number is not power of mux size
  > ad9081_fmca_ebz: enable xbar in DAC TPL
  > ad_ip_jesd204_tpl_dac: added xbar for user channels (dma data)
  > common/ad_mux: Pipelined mux, rtl and TB
  > up_dac_channel: add register for dma data xbar
  > ad9081_fmca_ebz/zc706: Initial version
  > ad9081_fmca_ebz: HP0 is already initialized in ZC706
  > daq3:zcu102: Connect overflow pins for the AD9680 TPL
  > adrv9009zu11eg/adrv2crr_fmc: Fix hmc7044_car_gpio connections

Signed-off-by: Michael Hennerich <[email protected]>