m32x: fix regs & reset state

ares-emulator · Feb 17, 2025 · a9f9fd9 · a9f9fd9
1 parent deb8830
commit a9f9fd9
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Showing 3 changed files with 14 additions and 6 deletions.
diff --git a/ares/md/m32x/io-external.cpp b/ares/md/m32x/io-external.cpp
@@ -35,7 +35,9 @@ auto M32X::readExternalIO(n1 upper, n1 lower, n24 address, n16 data) -> n16 {
     data.bit(0) = dreq.vram;
     data.bit(1) = dreq.dma;
     data.bit(2) = dreq.active;
+    data.bit(3,6) = 0;
     data.bit(7) = dreq.fifo.full();
+    data.bit(8,15) = 0;
   }
 
   //68K to SH2 DREQ source address
@@ -62,9 +64,18 @@ auto M32X::readExternalIO(n1 upper, n1 lower, n24 address, n16 data) -> n16 {
     data.byte(0) = dreq.length.byte(0);
   }
 
+  if(address == 0xa15114 ||
+     address == 0xa15116 ||
+     address == 0xa15118 ||
+     address == 0xa1511c ||
+     address == 0xa1511e) {
+    data = 0;
+  }
+
   //TV register
   if(address == 0xa1511a) {
     data.bit(0) = io.cartridgeMode;
+    data.bit(1,15) = 0;
   }
 
   //communication

diff --git a/ares/md/m32x/m32x.cpp b/ares/md/m32x/m32x.cpp
@@ -51,15 +51,12 @@ auto M32X::power(bool reset) -> void {
   shs.power(reset);
   vdp.power(reset);
   pwm.power(reset);
+  n32 vec4 = io.vectorLevel4;
   io = {};
+  if(reset) io.vectorLevel4 = vec4;
   dreq = {};
   for(auto& word : communication) word = 0;
 
-  io.vectorLevel4.byte(3) = vectors[0x70 >> 1].byte(1);
-  io.vectorLevel4.byte(2) = vectors[0x70 >> 1].byte(0);
-  io.vectorLevel4.byte(1) = vectors[0x72 >> 1].byte(1);
-  io.vectorLevel4.byte(0) = vectors[0x72 >> 1].byte(0);
-
   //connect interfaces
   shm.sci.link = shs;
   shs.sci.link = shm;

diff --git a/ares/md/m32x/m32x.hpp b/ares/md/m32x/m32x.hpp
@@ -218,7 +218,7 @@ struct M32X {
 
     //$a15000
     n1 adapterEnable;
-    n1 adapterReset;
+    n1 adapterReset = 1;
     n1 resetEnable = 1;
 
     //$a15004