-
Notifications
You must be signed in to change notification settings - Fork 3
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
- Loading branch information
1 parent
727c8a0
commit 694af1b
Showing
2 changed files
with
264 additions
and
0 deletions.
There are no files selected for viewing
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,264 @@ | ||
# | ||
# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. | ||
# | ||
# NVIDIA CORPORATION and its licensors retain all intellectual property | ||
# and proprietary rights in and to this software, related documentation | ||
# and any modifications thereto. Any use, reproduction, disclosure or | ||
# distribution of this software and related documentation without an express | ||
# license agreement from NVIDIA CORPORATION is strictly prohibited. | ||
# | ||
# FORMAT: | ||
# < PARAM TYPE=PARAM_TYPE NAME=PARAM_NAME > | ||
# ARG1_NAME ARG1_PATH_VAL | ||
# ARG2_NAME ARG2_PATH_VAL | ||
# ... | ||
# This starts a section of PARAM definitions, in which each line | ||
# has the syntax below: | ||
# ARG_NAME ARG_PATH_VAL | ||
# ARG_NAME is a macro name for argument value ARG_PATH_VAL. | ||
# PARAM_TYPE can be FILE, or CLOCK. | ||
# | ||
# < POWER_MODEL ID=id_num NAME=mode_name > | ||
# PARAM1_NAME ARG11_NAME ARG11_VAL | ||
# PARAM1_NAME ARG12_NAME ARG12_VAL | ||
# PARAM2_NAME ARG21_NAME ARG21_VAL | ||
# ... | ||
# This starts a section of POWER_MODEL configurations, followed by | ||
# lines with parameter settings as the format below: | ||
# PARAM_NAME ARG_NAME ARG_VAL | ||
# PARAM_NAME and ARG_NAME are defined in PARAM definition sections. | ||
# ARG_VAL is an integer for PARAM_TYPE of CLOCK, and -1 is taken | ||
# as INT_MAX. ARG_VAL is a string for PARAM_TYPE of FILE. | ||
# This file must contain at least one POWER_MODEL section. | ||
# | ||
# < PM_CONFIG DEFAULT=default_mode > | ||
# This is a mandatory section to specify one of the defined power | ||
# model as the default. | ||
|
||
########################### | ||
# # | ||
# PARAM DEFINITIONS # | ||
# # | ||
########################### | ||
|
||
< PARAM TYPE=FILE NAME=CPU_ONLINE > | ||
CORE_0 /sys/devices/system/cpu/cpu0/online | ||
CORE_1 /sys/devices/system/cpu/cpu1/online | ||
CORE_2 /sys/devices/system/cpu/cpu2/online | ||
CORE_3 /sys/devices/system/cpu/cpu3/online | ||
CORE_4 /sys/devices/system/cpu/cpu4/online | ||
CORE_5 /sys/devices/system/cpu/cpu5/online | ||
|
||
< PARAM TYPE=FILE NAME=TPC_POWER_GATING > | ||
TPC_PG_MASK /sys/devices/gpu.0/tpc_pg_mask | ||
|
||
< PARAM TYPE=FILE NAME=GPU_POWER_CONTROL_ENABLE > | ||
GPU_PWR_CNTL_EN /sys/devices/gpu.0/power/control | ||
|
||
< PARAM TYPE=FILE NAME=GPU_POWER_CONTROL_DISABLE > | ||
GPU_PWR_CNTL_DIS /sys/devices/gpu.0/power/control | ||
|
||
< PARAM TYPE=CLOCK NAME=CPU_DENVER_0 > | ||
FREQ_TABLE /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies | ||
MAX_FREQ /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq | ||
MIN_FREQ /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq | ||
FREQ_TABLE_KNEXT /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies | ||
MAX_FREQ_KNEXT /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq | ||
MIN_FREQ_KNEXT /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq | ||
|
||
< PARAM TYPE=CLOCK NAME=CPU_DENVER_1 > | ||
FREQ_TABLE /sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies | ||
MAX_FREQ /sys/devices/system/cpu/cpu2/cpufreq/scaling_max_freq | ||
MIN_FREQ /sys/devices/system/cpu/cpu2/cpufreq/scaling_min_freq | ||
FREQ_TABLE_KNEXT /sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies | ||
MAX_FREQ_KNEXT /sys/devices/system/cpu/cpu2/cpufreq/scaling_max_freq | ||
MIN_FREQ_KNEXT /sys/devices/system/cpu/cpu2/cpufreq/scaling_min_freq | ||
|
||
< PARAM TYPE=CLOCK NAME=CPU_DENVER_2 > | ||
FREQ_TABLE /sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies | ||
MAX_FREQ /sys/devices/system/cpu/cpu4/cpufreq/scaling_max_freq | ||
MIN_FREQ /sys/devices/system/cpu/cpu4/cpufreq/scaling_min_freq | ||
FREQ_TABLE_KNEXT /sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies | ||
MAX_FREQ_KNEXT /sys/devices/system/cpu/cpu4/cpufreq/scaling_max_freq | ||
MIN_FREQ_KNEXT /sys/devices/system/cpu/cpu4/cpufreq/scaling_min_freq | ||
|
||
< PARAM TYPE=CLOCK NAME=GPU > | ||
FREQ_TABLE /sys/devices/17000000.gv11b/devfreq/17000000.gv11b/available_frequencies | ||
MAX_FREQ /sys/devices/17000000.gv11b/devfreq/17000000.gv11b/max_freq | ||
MIN_FREQ /sys/devices/17000000.gv11b/devfreq/17000000.gv11b/min_freq | ||
FREQ_TABLE_KNEXT /sys/devices/17000000.gv11b/devfreq/devfreq0/available_frequencies | ||
MAX_FREQ_KNEXT /sys/devices/17000000.gv11b/devfreq/devfreq0/max_freq | ||
MIN_FREQ_KNEXT /sys/devices/17000000.gv11b/devfreq/devfreq0/min_freq | ||
|
||
< PARAM TYPE=CLOCK NAME=EMC > | ||
MAX_FREQ /sys/kernel/nvpmodel_emc_cap/emc_iso_cap | ||
MAX_FREQ_KNEXT /sys/kernel/nvpmodel_emc_cap/emc_iso_cap | ||
|
||
< PARAM TYPE=CLOCK NAME=DLA_CORE > | ||
MAX_FREQ /sys/kernel/nvpmodel_emc_cap/nafll_dla | ||
MAX_FREQ_KNEXT /sys/kernel/nvpmodel_emc_cap/nafll_dla | ||
|
||
< PARAM TYPE=CLOCK NAME=DLA_FALCON > | ||
MAX_FREQ /sys/kernel/nvpmodel_emc_cap/nafll_dla_falcon | ||
MAX_FREQ_KNEXT /sys/kernel/nvpmodel_emc_cap/nafll_dla_falcon | ||
|
||
< PARAM TYPE=CLOCK NAME=PVA_VPS > | ||
MAX_FREQ /sys/kernel/nvpmodel_emc_cap/nafll_pva_vps | ||
MAX_FREQ_KNEXT /sys/kernel/nvpmodel_emc_cap/nafll_pva_vps | ||
|
||
< PARAM TYPE=CLOCK NAME=PVA_CORE > | ||
MAX_FREQ /sys/kernel/nvpmodel_emc_cap/nafll_pva_core | ||
MAX_FREQ_KNEXT /sys/kernel/nvpmodel_emc_cap/nafll_pva_core | ||
|
||
< PARAM TYPE=CLOCK NAME=CVNAS > | ||
MAX_FREQ /sys/kernel/nvpmodel_emc_cap/nafll_cvnas | ||
MAX_FREQ_KNEXT /sys/kernel/nvpmodel_emc_cap/nafll_cvnas | ||
|
||
########################### | ||
# # | ||
# POWER_MODEL DEFINITIONS # | ||
# # | ||
########################### | ||
|
||
< POWER_MODEL ID=0 NAME=MAXN > | ||
CPU_ONLINE CORE_0 1 | ||
CPU_ONLINE CORE_1 1 | ||
CPU_ONLINE CORE_2 1 | ||
CPU_ONLINE CORE_3 1 | ||
CPU_ONLINE CORE_4 1 | ||
CPU_ONLINE CORE_5 1 | ||
TPC_POWER_GATING TPC_PG_MASK 1 | ||
GPU_POWER_CONTROL_ENABLE GPU_PWR_CNTL_EN on | ||
CPU_DENVER_0 MIN_FREQ 1190400 | ||
CPU_DENVER_0 MAX_FREQ 1907200 | ||
CPU_DENVER_1 MIN_FREQ 1190400 | ||
CPU_DENVER_1 MAX_FREQ 1907200 | ||
CPU_DENVER_2 MIN_FREQ 1190400 | ||
CPU_DENVER_2 MAX_FREQ 1907200 | ||
GPU MIN_FREQ 0 | ||
GPU MAX_FREQ 1109250000 | ||
GPU_POWER_CONTROL_DISABLE GPU_PWR_CNTL_DIS auto | ||
EMC MAX_FREQ 1600000000 | ||
DLA_CORE MAX_FREQ 1100800000 | ||
DLA_FALCON MAX_FREQ 640000000 | ||
PVA_VPS MAX_FREQ 819200000 | ||
PVA_CORE MAX_FREQ 814000000 | ||
CVNAS MAX_FREQ 576000000 | ||
|
||
< POWER_MODEL ID=1 NAME=MODE_15W_2CORE > | ||
CPU_ONLINE CORE_0 1 | ||
CPU_ONLINE CORE_1 1 | ||
CPU_ONLINE CORE_2 0 | ||
CPU_ONLINE CORE_3 0 | ||
CPU_ONLINE CORE_4 0 | ||
CPU_ONLINE CORE_5 0 | ||
TPC_POWER_GATING TPC_PG_MASK 1 | ||
GPU_POWER_CONTROL_ENABLE GPU_PWR_CNTL_EN on | ||
CPU_DENVER_0 MIN_FREQ 1190400 | ||
CPU_DENVER_0 MAX_FREQ 1907200 | ||
GPU MIN_FREQ 0 | ||
GPU MAX_FREQ 1109250000 | ||
GPU_POWER_CONTROL_DISABLE GPU_PWR_CNTL_DIS auto | ||
EMC MAX_FREQ 1600000000 | ||
DLA_CORE MAX_FREQ 1100800000 | ||
DLA_FALCON MAX_FREQ 640000000 | ||
PVA_VPS MAX_FREQ 819200000 | ||
PVA_CORE MAX_FREQ 601600000 | ||
CVNAS MAX_FREQ 576000000 | ||
|
||
< POWER_MODEL ID=2 NAME=MODE_15W_4CORE > | ||
CPU_ONLINE CORE_0 1 | ||
CPU_ONLINE CORE_1 1 | ||
CPU_ONLINE CORE_2 1 | ||
CPU_ONLINE CORE_3 1 | ||
CPU_ONLINE CORE_4 0 | ||
CPU_ONLINE CORE_5 0 | ||
TPC_POWER_GATING TPC_PG_MASK 1 | ||
GPU_POWER_CONTROL_ENABLE GPU_PWR_CNTL_EN on | ||
CPU_DENVER_0 MIN_FREQ 1190400 | ||
CPU_DENVER_0 MAX_FREQ 1420800 | ||
CPU_DENVER_1 MIN_FREQ 1190400 | ||
CPU_DENVER_1 MAX_FREQ 1420800 | ||
GPU MIN_FREQ 0 | ||
GPU MAX_FREQ 1109250000 | ||
GPU_POWER_CONTROL_DISABLE GPU_PWR_CNTL_DIS auto | ||
EMC MAX_FREQ 1600000000 | ||
DLA_CORE MAX_FREQ 1100800000 | ||
DLA_FALCON MAX_FREQ 640000000 | ||
PVA_VPS MAX_FREQ 819200000 | ||
PVA_CORE MAX_FREQ 601600000 | ||
CVNAS MAX_FREQ 576000000 | ||
|
||
< POWER_MODEL ID=3 NAME=MODE_15W_6CORE > | ||
CPU_ONLINE CORE_0 1 | ||
CPU_ONLINE CORE_1 1 | ||
CPU_ONLINE CORE_2 1 | ||
CPU_ONLINE CORE_3 1 | ||
CPU_ONLINE CORE_4 1 | ||
CPU_ONLINE CORE_5 1 | ||
TPC_POWER_GATING TPC_PG_MASK 1 | ||
GPU_POWER_CONTROL_ENABLE GPU_PWR_CNTL_EN on | ||
CPU_DENVER_0 MIN_FREQ 1190400 | ||
CPU_DENVER_0 MAX_FREQ 1420800 | ||
CPU_DENVER_1 MIN_FREQ 1190400 | ||
CPU_DENVER_1 MAX_FREQ 1420800 | ||
CPU_DENVER_2 MIN_FREQ 1190400 | ||
CPU_DENVER_2 MAX_FREQ 1420800 | ||
GPU MIN_FREQ 0 | ||
GPU MAX_FREQ 1109250000 | ||
GPU_POWER_CONTROL_DISABLE GPU_PWR_CNTL_DIS auto | ||
EMC MAX_FREQ 1600000000 | ||
DLA_CORE MAX_FREQ 1100800000 | ||
DLA_FALCON MAX_FREQ 640000000 | ||
PVA_VPS MAX_FREQ 819200000 | ||
PVA_CORE MAX_FREQ 601600000 | ||
CVNAS MAX_FREQ 576000000 | ||
|
||
< POWER_MODEL ID=4 NAME=MODE_10W_2CORE > | ||
CPU_ONLINE CORE_0 1 | ||
CPU_ONLINE CORE_1 1 | ||
CPU_ONLINE CORE_2 0 | ||
CPU_ONLINE CORE_3 0 | ||
CPU_ONLINE CORE_4 0 | ||
CPU_ONLINE CORE_5 0 | ||
TPC_POWER_GATING TPC_PG_MASK 1 | ||
GPU_POWER_CONTROL_ENABLE GPU_PWR_CNTL_EN on | ||
CPU_DENVER_0 MIN_FREQ 1190400 | ||
CPU_DENVER_0 MAX_FREQ 1497600 | ||
GPU MIN_FREQ 0 | ||
GPU MAX_FREQ 803250000 | ||
GPU_POWER_CONTROL_DISABLE GPU_PWR_CNTL_DIS auto | ||
EMC MAX_FREQ 1600000000 | ||
DLA_CORE MAX_FREQ 896000000 | ||
DLA_FALCON MAX_FREQ 524800000 | ||
PVA_VPS MAX_FREQ 550400000 | ||
PVA_CORE MAX_FREQ 409600000 | ||
CVNAS MAX_FREQ 460800000 | ||
|
||
< POWER_MODEL ID=5 NAME=MODE_10W_4CORE > | ||
CPU_ONLINE CORE_0 1 | ||
CPU_ONLINE CORE_1 1 | ||
CPU_ONLINE CORE_2 1 | ||
CPU_ONLINE CORE_3 1 | ||
CPU_ONLINE CORE_4 0 | ||
CPU_ONLINE CORE_5 0 | ||
TPC_POWER_GATING TPC_PG_MASK 1 | ||
GPU_POWER_CONTROL_ENABLE GPU_PWR_CNTL_EN on | ||
CPU_DENVER_0 MIN_FREQ 1190400 | ||
CPU_DENVER_0 MAX_FREQ 1190400 | ||
CPU_DENVER_1 MIN_FREQ 1190400 | ||
CPU_DENVER_1 MAX_FREQ 1190400 | ||
GPU MIN_FREQ 0 | ||
GPU MAX_FREQ 803250000 | ||
GPU_POWER_CONTROL_DISABLE GPU_PWR_CNTL_DIS auto | ||
EMC MAX_FREQ 1600000000 | ||
DLA_CORE MAX_FREQ 896000000 | ||
DLA_FALCON MAX_FREQ 524800000 | ||
PVA_VPS MAX_FREQ 550400000 | ||
PVA_CORE MAX_FREQ 409600000 | ||
CVNAS MAX_FREQ 460800000 | ||
|
||
# mandatory section to configure the default power mode | ||
< PM_CONFIG DEFAULT=3 > | ||
# optional section to configure the default fan mode | ||
< FAN_CONFIG DEFAULT=quiet > |