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Arm regressions #2556

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merged 6 commits into from
Dec 5, 2024
Merged

Arm regressions #2556

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0a40018
Fix: Set writeback for AddrMode5 operands with W=1
Rot127 Nov 25, 2024
7c8c7a5
Fix memory acccess of vector load instructions.
Rot127 Nov 25, 2024
80e9a45
Remove unused files.
Rot127 Nov 25, 2024
b5a6457
Fix operands of RFED instructions
Rot127 Nov 25, 2024
d1ff557
Fix: Remove invalid mnemonic enum adr_
Rot127 Nov 25, 2024
cd14f76
Add missing NULL check
Rot127 Nov 26, 2024
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8 changes: 4 additions & 4 deletions arch/ARM/ARMGenCSMappingInsn.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -26955,15 +26955,15 @@
},
{
/* vscclrm{$p} $regs */
ARM_VSCCLRMD /* 3449 */, ARM_INS_VSCCLRM_,
ARM_VSCCLRMD /* 3449 */, ARM_INS_VSCCLRM,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_FEATURE_HASV8_1MMAINLINE, ARM_FEATURE_HAS8MSECEXT, 0 }, 0, 0, { .aarch64 = { .mem_acc = CS_AC_INVALID }}

#endif
},
{
/* vscclrm{$p} $regs */
ARM_VSCCLRMS /* 3450 */, ARM_INS_VSCCLRM_,
ARM_VSCCLRMS /* 3450 */, ARM_INS_VSCCLRM,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_FEATURE_HASV8_1MMAINLINE, ARM_FEATURE_HAS8MSECEXT, 0 }, 0, 0, { .aarch64 = { .mem_acc = CS_AC_INVALID }}

Expand Down Expand Up @@ -31147,7 +31147,7 @@
},
{
/* adr{$p}.w $Rd, $addr */
ARM_t2ADR /* 3989 */, ARM_INS_ADR_,
ARM_t2ADR /* 3989 */, ARM_INS_ADR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_FEATURE_ISTHUMB2, 0 }, 0, 0, { .aarch64 = { .mem_acc = CS_AC_INVALID }}

Expand Down Expand Up @@ -34319,7 +34319,7 @@
},
{
/* adr{$p} $Rd, $addr */
ARM_tADR /* 4386 */, ARM_INS_ADR_,
ARM_tADR /* 4386 */, ARM_INS_ADR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_FEATURE_ISTHUMB, 0 }, 0, 0, { .aarch64 = { .mem_acc = CS_AC_INVALID }}

Expand Down
3 changes: 1 addition & 2 deletions arch/ARM/ARMGenCSMappingInsnName.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -577,7 +577,7 @@
"vrsqrts", // ARM_INS_VRSQRTS
"vrsra", // ARM_INS_VRSRA
"vrsubhn", // ARM_INS_VRSUBHN
"vscclrm_", // ARM_INS_VSCCLRM_
"vscclrm", // ARM_INS_VSCCLRM
"vsdot", // ARM_INS_VSDOT
"vseleq", // ARM_INS_VSELEQ
"vselge", // ARM_INS_VSELGE
Expand Down Expand Up @@ -608,7 +608,6 @@
"vuzp", // ARM_INS_VUZP
"vzip", // ARM_INS_VZIP
"addw", // ARM_INS_ADDW
"adr_", // ARM_INS_ADR_
"aut", // ARM_INS_AUT
"autg", // ARM_INS_AUTG
"bfl", // ARM_INS_BFL
Expand Down
8 changes: 4 additions & 4 deletions arch/ARM/ARMGenCSMappingInsnOp.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -28521,15 +28521,15 @@
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
{ 0 }
}},
{ /* ARM_VSCCLRMD (3449) - ARM_INS_VSCCLRM_ - vscclrm{$p} $regs */
{ /* ARM_VSCCLRMD (3449) - ARM_INS_VSCCLRM - vscclrm{$p} $regs */
{
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
{ CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
{ CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */
{ 0 }
}},
{ /* ARM_VSCCLRMS (3450) - ARM_INS_VSCCLRM_ - vscclrm{$p} $regs */
{ /* ARM_VSCCLRMS (3450) - ARM_INS_VSCCLRM - vscclrm{$p} $regs */
{
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
Expand Down Expand Up @@ -32923,7 +32923,7 @@
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
{ 0 }
}},
{ /* ARM_t2ADR (3989) - ARM_INS_ADR_ - adr{$p}.w $Rd, $addr */
{ /* ARM_t2ADR (3989) - ARM_INS_ADR - adr{$p}.w $Rd, $addr */
{
{ CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
Expand Down Expand Up @@ -36491,7 +36491,7 @@
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
{ 0 }
}},
{ /* ARM_tADR (4386) - ARM_INS_ADR_ - adr{$p} $Rd, $addr */
{ /* ARM_tADR (4386) - ARM_INS_ADR - adr{$p} $Rd, $addr */
{
{ CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
Expand Down
59 changes: 38 additions & 21 deletions arch/ARM/ARMMapping.c
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Original file line number Diff line number Diff line change
Expand Up @@ -565,6 +565,20 @@ static void ARM_add_not_defined_ops(MCInst *MI)
}
break;
}
case ARM_RFEDA_UPD:
case ARM_RFEDB_UPD:
case ARM_RFEIA_UPD:
case ARM_RFEIB_UPD:
get_detail(MI)->writeback = true;
// fallthrough
case ARM_RFEDA:
case ARM_RFEDB:
case ARM_RFEIA:
case ARM_RFEIB: {
arm_reg base_reg = ARM_get_detail_op(MI, -1)->reg;
ARM_get_detail_op(MI, -1)->type = ARM_OP_MEM;
ARM_get_detail_op(MI, -1)->mem.base = base_reg;
}
}
}

Expand Down Expand Up @@ -627,6 +641,26 @@ static void ARM_post_index_detection(MCInst *MI)
ARM_dec_op_count(MI);
}

void ARM_check_mem_access_validity(MCInst *MI)
{
#ifndef CAPSTONE_DIET
if (!detail_is_set(MI))
return;
const arm_suppl_info *suppl = map_get_suppl_info(MI, arm_insns);
CS_ASSERT_RET(suppl);
if (suppl->mem_acc == CS_AC_INVALID) {
return;
}
cs_detail *detail = get_detail(MI);
for (int i = 0; i < detail->arm.op_count; ++i) {
if (detail->arm.operands[i].type == ARM_OP_MEM && detail->arm.operands[i].access != suppl->mem_acc) {
detail->arm.operands[i].access = suppl->mem_acc;
return;
}
}
#endif // CAPSTONE_DIET
}

/// Decodes the asm string for a given instruction
/// and fills the detail information about the instruction and its operands.
void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
Expand All @@ -639,6 +673,7 @@ void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
map_set_alias_id(MI, O, insn_alias_mnem_map, ARR_SIZE(insn_alias_mnem_map) - 1);
ARM_add_not_defined_ops(MI);
ARM_post_index_detection(MI);
ARM_check_mem_access_validity(MI);
ARM_add_cs_groups(MI);
int syntax_opt = MI->csh->syntax;
if (syntax_opt & CS_OPT_SYNTAX_CS_REG_ALIAS)
Expand Down Expand Up @@ -767,32 +802,12 @@ void ARM_check_updates_flags(MCInst *MI)
#endif // CAPSTONE_DIET
}

void ARM_check_mem_access_validity(MCInst *MI)
{
#ifndef CAPSTONE_DIET
if (!detail_is_set(MI))
return;
const arm_suppl_info *suppl = map_get_suppl_info(MI, arm_insns);
if (suppl->mem_acc == CS_AC_INVALID) {
return;
}
cs_detail *detail = get_detail(MI);
for (int i = 0; i < detail->arm.op_count; ++i) {
if (detail->arm.operands[i].type == ARM_OP_MEM && detail->arm.operands[i].access != suppl->mem_acc) {
detail->arm.operands[i].access = suppl->mem_acc;
return;
}
}
#endif // CAPSTONE_DIET
}

void ARM_set_instr_map_data(MCInst *MI)
{
map_cs_id(MI, arm_insns, ARR_SIZE(arm_insns));
map_implicit_reads(MI, arm_insns);
map_implicit_writes(MI, arm_insns);
ARM_check_updates_flags(MI);
ARM_check_mem_access_validity(MI);
map_groups(MI, arm_insns);
}

Expand Down Expand Up @@ -1848,8 +1863,10 @@ static void add_cs_detail_template_1(MCInst *MI, arm_op_group op_group,
case ARM_OP_GROUP_AddrMode5FP16Operand_0: {
bool AlwaysPrintImm0 = temp_arg_0;

if (AlwaysPrintImm0)
if (AlwaysPrintImm0) {
get_detail(MI)->writeback = true;
map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum));
}

ARM_check_safe_inc(MI);
cs_arm_op *Op = ARM_get_detail_op(MI, 0);
Expand Down
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