Implemented the allocate function for the Page Level Allocator and re…

…placed UAddr with usize since the latter is always a pointer sized unsigned integer which is what UAddr was meant to be anyway.

charlotte_core/src/arch/mod.rs

@@ -11,7 +11,7 @@ use core::result::Result;
 use spin::{lazy::Lazy, mutex::TicketMutex};
 
 use crate::framebuffer::console::CONSOLE;
-use crate::memory::address::{PhysicalAddress, UAddr, VirtualAddress};
+use crate::memory::address::{PhysicalAddress, VirtualAddress};
 
 #[cfg(target_arch = "aarch64")]
 pub mod aarch64;
@@ -118,7 +118,7 @@ pub trait MemoryMap {
     fn find_available_region(
         &self,
         size: NonZeroUsize,
-        alignment: UAddr,
+        alignment: usize,
         start: VirtualAddress,
         end: VirtualAddress,
     ) -> Result<VirtualAddress, Self::Error>;
@@ -133,6 +133,13 @@ pub struct IsaParams {
     pub paging: PagingParams,
 }
 
+#[derive(Debug, Copy, Clone)]
+pub struct PagingParams {
+    pub page_size: usize,
+    pub page_shift: usize,
+    pub page_mask: usize,
+}
+
 pub trait Api {
     type Api: Api;
     type DebugLogger: Write;
@@ -144,6 +151,7 @@ pub trait Api {
     /// * [X86_64](x86_64::Api::isa_init)
     fn isa_init() -> Self;
 
+    fn get_memory_map() -> Self::MemoryMap;
     fn get_logger() -> Self::DebugLogger;
     fn get_serial(&self) -> Self::Serial;
     fn get_paddr_width() -> u8;
@@ -217,8 +225,8 @@ pub type ArchApi = aarch64::Api;
 pub type ArchApi = riscv64::Api;
 
 #[cfg(target_arch = "x86_64")]
-pub const ISA_PARAMS: IsaParams = x86_64::X86_ISA_PARAMS;
+pub const ISA_PARAMS: IsaParams = x86_64::ISA_PARAMS;
 #[cfg(target_arch = "aarch64")]
-pub static MEMORY_PARAMS: PagingParams = aarch64::ISA_MEMORY_PARAMS;
+pub static ISA_PARAMS: IsaParams = aarch64::ISA_PARAMS;
 #[cfg(target_arch = "riscv64")]
-pub static MEMORY_PARAMS: PagingParams = riscv64::ISA_MEMORY_PARAMS;
+pub static ISA_PARAMS: IsaParams = riscv64::ISA_PARAMS;

charlotte_core/src/arch/x86_64/memory/page_map/mod.rs

@@ -13,7 +13,7 @@ use core::ptr::addr_of_mut;
 use crate::arch::x86_64::cpu::ARE_HUGE_PAGES_SUPPORTED;
 use crate::arch::{Api, ArchApi, MemoryMap};
 use crate::logln;
-use crate::memory::address::{MemoryAddress, UAddr, VirtualAddress};
+use crate::memory::address::{MemoryAddress, VirtualAddress};
 use crate::memory::{address::PhysicalAddress, pmm::PHYSICAL_FRAME_ALLOCATOR};
 
 static N_FRAMES_PDPT: usize = 512 * 512;
@@ -137,7 +137,7 @@ impl PageMap {
         }
     }
     pub fn get_pml4_paddr(&self) -> PhysicalAddress {
-        PhysicalAddress::from(self.cr3 & !0xFFF)
+        PhysicalAddress::from((self.cr3 & !0xFFF) as usize)
     }
     pub fn get_pcid(&self) -> u16 {
         (self.cr3 & 0xFFF) as u16
@@ -219,21 +219,21 @@ impl MemoryMap for PageMap {
     fn get_flags(mem_type: crate::arch::MemType) -> Self::Flags {
         match mem_type {
             crate::arch::MemType::KernelReadWrite => {
-                PteFlags::PRESENT as u64
-                | PteFlags::WRITABLE as u64
-                | PteFlags::NO_EXECUTE as u64
-                | PteFlags::GLOBAL as u64
+                PteFlags::Present as u64
+                | PteFlags::Write as u64
+                | PteFlags::NoExecute as u64
+                | PteFlags::Global as u64
                 | PteFlags::WriteThrough as u64
             },
             crate::arch::MemType::KernelReadOnly => {
-                PteFlags::PRESENT as u64
-                | PteFlags::NO_EXECUTE as u64
-                | PteFlags::GLOBAL as u64
+                PteFlags::Present as u64
+                | PteFlags::NoExecute as u64
+                | PteFlags::Global as u64
                 | PteFlags::WriteThrough as u64
             },
             crate::arch::MemType::KernelReadExecute => {
-                PteFlags::PRESENT as u64
-                | PteFlags::GLOBAL as u64
+                PteFlags::Present as u64
+                | PteFlags::Global as u64
                 | PteFlags::WriteThrough as u64
             },
         }
@@ -401,7 +401,7 @@ impl MemoryMap for PageMap {
     fn find_available_region(
         &self,
         size: NonZeroUsize,
-        alignment: UAddr,
+        alignment: usize,
         start: VirtualAddress,
         end: VirtualAddress,
     ) -> Result<VirtualAddress, Self::Error> {

charlotte_core/src/arch/x86_64/memory/page_map/page_table/mod.rs

@@ -23,8 +23,8 @@ pub enum PageTableLevel {
 }
 
 const N_PT_ENTRIES: usize = 512;
-const LARGE_PAGE_NFRAMES: u64 = 512;
-const HUGE_PAGE_NFRAMES: u64 = 512 * 512;
+const LARGE_PAGE_NFRAMES: usize = 512;
+const HUGE_PAGE_NFRAMES: usize = 512 * 512;
 
 #[repr(C, align(4096))]
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]

charlotte_core/src/arch/x86_64/memory/page_map/page_table/page_table_entry.rs

@@ -60,7 +60,7 @@ impl PageTableEntry {
         if self.is_present() == false {
             Err(Error::EntryNotPresent)
         } else {
-            Ok(PhysicalAddress::from(self.entry & *ADDR_MASK))
+            Ok(PhysicalAddress::from((self.entry & *ADDR_MASK) as usize))
         }
     }
 
@@ -70,7 +70,7 @@ impl PageTableEntry {
         } else if !paddr.is_page_aligned() {
             Err(Error::InvalidPAddrAlignment)
         } else {
-            self.entry = (paddr.bits() & *ADDR_MASK) | (flags & FLAG_MASK);
+            self.entry = (paddr.bits() as u64 & *ADDR_MASK) | (flags & FLAG_MASK);
             Ok(())
         }
     }
@@ -91,7 +91,7 @@ impl PageTableEntry {
             } else {
                 HUGE_AND_LARGE_PAGE_FLAG_MASK
             };
-            self.entry = (paddr.bits() & *ADDR_MASK) | (flags & flag_mask);
+            self.entry = (paddr.bits() as u64 & *ADDR_MASK) | (flags & flag_mask);
             Ok(())
         }
     }

charlotte_core/src/arch/x86_64/mod.rs

@@ -49,7 +49,7 @@ static BSP_RING0_INT_STACK: [u8; 4096] = [0u8; 4096];
 static BSP_TSS: Lazy<Tss> = Lazy::new(|| Tss::new(addr_of!(BSP_RING0_INT_STACK) as u64));
 static BSP_GDT: Lazy<Gdt> = Lazy::new(|| Gdt::new(&BSP_TSS));
 static BSP_IDT: SpinMutex<Idt> = SpinMutex::new(Idt::new());
-pub const X86_ISA_PARAMS: IsaParams = IsaParams {
+pub const ISA_PARAMS: IsaParams = IsaParams {
     paging: PagingParams {
         page_size: 0x1000,
         page_shift: 0xC,
@@ -98,6 +98,12 @@ impl crate::arch::Api for Api {
         api
     }
 
+    #[inline]
+    fn get_memory_map() -> Self::MemoryMap {
+        memory::page_map::PageMap::from_cr3(memory::page_map::get_cr3())
+            .expect("unable to create a page map structure from the address in the current CR3 value")
+    }
+
     /// Get a new logger instance
     fn get_logger() -> Self::DebugLogger {
         SerialPort::try_new(ComPort::COM1).unwrap()
@@ -327,7 +333,7 @@ impl Api {
         };
 
         //map to the beginning of the higher half of the virtual address space i.e. the beginning of kernelspace
-        let vaddr = match VirtualAddress::try_from(0xFFFF800000000000) {
+        let vaddr = match VirtualAddress::try_from(0xFFFF800000000000usize) {
             Ok(vaddr) => vaddr,
             Err(e) => {
                 panic!("Failed to create VirtualAddress: {:?}", e);