Mark return value of .asTypeOf as "deprecated read-only"

[jackkoenig]

Users will now get a deprecation warning if they connect to the result of .asTypeOf.

Marked for backporting to 6.x so that we can change this in 7.0.

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
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Type of Improvement

• API deprecation

Desired Merge Strategy

• Squash

Release Notes

Previously, .asTypeOf would return a Wire. To get the old behavior, wrap the .asTypeOf call in WireInit(...).

Reviewer Checklist (only modified by reviewer)

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[jackkoenig]

This change to the .fir is unfortunate, I will look into this later (perhaps we need naming to contemplate views).

[seldridge]

LGTM

[sequencer]

This PR introduced bug to T1. Related code snippet:

  val slotControl: Vec[InstructionControlRecord] =
    RegInit(
      VecInit(
        Seq.fill(parameter.chainingSize)(0.U.asTypeOf(new InstructionControlRecord(parameter)))
      )
    )

error message:

Caused by: chisel3.package$ChiselException: Connection between left (Lane.slotControl_?[0]: Wire[InstructionControlRecord]) and source (Lane.slotControl_?: Wire[InstructionControlRecord]) failed @.mask.bits: Locally unclear whether Left or Right (both internal)

[jackkoenig]

Thanks for the report, looking into it!

[jackkoenig]

This issue is caused by a weird interaction between how VecInit and directionality work. VecInit picks <> if the source is bidirectional¹, which then due to the specialized logic to sometimes emit FIRRTL bulk connects, will emit a FIRRTL bulk connect in this case². This PR broke that because it is conservative and won't issue bulk connections if either side is marked read-only³. That could change, we could still issue the bulk connect, but the real issue is actually #4204. The direction of your InstructionControlRecord is being reported as Bidirectional(Default) even though it isn't bidirectional due to the bug in the linked issue. So I'm going to fix that.

Footnotes

1. https://github.com/chipsalliance/chisel/blob/00c7a6288386b237be45fe471e67d9b9cc3192a4/core/src/main/scala/chisel3/Aggregate.scala#L646 ↩

2. https://github.com/chipsalliance/chisel/blob/00c7a6288386b237be45fe471e67d9b9cc3192a4/core/src/main/scala/chisel3/internal/BiConnect.scala#L196 ↩

3. https://github.com/chipsalliance/chisel/blob/00c7a6288386b237be45fe471e67d9b9cc3192a4/core/src/main/scala/chisel3/internal/BiConnect.scala#L133 ↩