Merge branch 'master' into 1.5-release

.mergify.yml

@@ -1,3 +1,7 @@
+queue_rules:
+- name: default
+  conditions:
+  - status-success=all tests passed
 pull_request_rules:
 - name: automatic squash-and-merge on CI success and review
   conditions:
@@ -9,10 +13,10 @@ pull_request_rules:
   - label!="DO NOT MERGE"
   - label!="bp-conflict"
   actions:
-    merge:
+    queue:
+      name: default
       method: squash
-      strict: smart
-      strict_method: merge
+      update_method: merge
 - name: backport to 1.4.x
   conditions:
   - merged
@@ -73,10 +77,10 @@ pull_request_rules:
   - label!="DO NOT MERGE"
   - label!="bp-conflict"
   actions:
-    merge:
+    queue:
+      name: default
       method: squash
-      strict: smart
-      strict_method: merge
+      update_method: merge
 - name: automatic squash-and-mege of 1.3.x backport PRs
   conditions:
   - status-success=all tests passed
@@ -86,10 +90,10 @@ pull_request_rules:
   - label!="DO NOT MERGE"
   - label!="bp-conflict"
   actions:
-    merge:
+    queue:
+      name: default
       method: squash
-      strict: smart
-      strict_method: merge
+      update_method: merge
 - name: automatic squash-and-mege of 1.4.x backport PRs
   conditions:
   - status-success=all tests passed
@@ -99,8 +103,8 @@ pull_request_rules:
   - label!="DO NOT MERGE"
   - label!="bp-conflict"
   actions:
-    merge:
+    queue:
+      name: default
       method: squash
-      strict: smart
-      strict_method: merge
+      update_method: merge
 

src/main/scala/firrtl/AddDescriptionNodes.scala

@@ -151,7 +151,7 @@ class AddDescriptionNodes extends Transform with DependencyAPIMigration {
       Dependency[firrtl.transforms.InlineBitExtractionsTransform],
       Dependency[firrtl.transforms.PropagatePresetAnnotations],
       Dependency[firrtl.transforms.InlineAcrossCastsTransform],
-      Dependency[firrtl.transforms.LegalizeClocksTransform],
+      Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform],
       Dependency[firrtl.transforms.FlattenRegUpdate],
       Dependency(passes.VerilogModulusCleanup),
       Dependency[firrtl.transforms.VerilogRename],

src/main/scala/firrtl/Emitter.scala

@@ -200,7 +200,7 @@ object EmitAllModulesAnnotation extends HasShellOptions {
         s.split(",")
           .map {
             case "disableMemRandomization" =>
-              CustomDefaultRegisterEmission(useInitAsPreset = true, disableRandomization = true)
+              CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
             case "disableRegisterRandomization" => CustomDefaultMemoryEmission(MemoryNoInit)
             case a                              => throw new PhaseException(s"Unknown emission options '$a'! (Did you misspell it?)")
           }

src/main/scala/firrtl/backends/experimental/rtlil/RtlilEmitter.scala

@@ -880,6 +880,8 @@ private[firrtl] class RtlilEmitter extends SeqTransform with Emitter with Depend
               println("Leaving memory uninitialized.")
             case MemoryFileInlineInit(_, _) =>
               throw EmitterException(s"Memory $name cannot be initialized from a file, RTLIL cannot express this.")
+            case MemoryNoInit =>
+            // No initialization to emit
           }
           for (r <- rd) {
             val data = memPortField(x, r, "data")

src/main/scala/firrtl/backends/experimental/smt/FirrtlExpressionSemantics.scala

@@ -13,7 +13,9 @@ private object FirrtlExpressionSemantics {
       case ir.DoPrim(op, args, consts, _) => onPrim(op, args, consts)
       case r: ir.RefLikeExpression => BVSymbol(r.serialize, getWidth(r))
       case ir.UIntLiteral(value, ir.IntWidth(width)) => BVLiteral(value, width.toInt)
-      case ir.SIntLiteral(value, ir.IntWidth(width)) => BVLiteral(value, width.toInt)
+      case ir.SIntLiteral(value, ir.IntWidth(width)) =>
+        val twosComplementValue = value & ((BigInt(1) << width.toInt) - 1)
+        BVLiteral(twosComplementValue, width.toInt)
       case ir.Mux(cond, tval, fval, _) =>
         val width = List(tval, fval).map(getWidth).max
         BVIte(toSMT(cond), toSMT(tval, width), toSMT(fval, width))

src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala

@@ -787,13 +787,12 @@ class VerilogEmitter extends SeqTransform with Emitter {
       } else { // Asynchronous Reset
         assert(reset.tpe == AsyncResetType, "Error! Synchronous reset should have been removed!")
         val tv = init
-        val InfoExpr(finfo, fv) = netlist(r)
-        // TODO add register info argument and build a MultiInfo to pass
+        val InfoExpr(info, fv) = netlist(r)
         asyncResetAlwaysBlocks += (
           (
             clk,
             reset,
-            addUpdate(NoInfo, Mux(reset, tv, fv, mux_type_and_widths(tv, fv)), Seq.empty)
+            addUpdate(info, Mux(reset, tv, fv, mux_type_and_widths(tv, fv)), Seq.empty)
           )
         )
       }

src/main/scala/firrtl/passes/VerilogModulusCleanup.scala

@@ -33,7 +33,7 @@ object VerilogModulusCleanup extends Pass {
       Dependency[firrtl.transforms.ReplaceTruncatingArithmetic],
       Dependency[firrtl.transforms.InlineBitExtractionsTransform],
       Dependency[firrtl.transforms.InlineAcrossCastsTransform],
-      Dependency[firrtl.transforms.LegalizeClocksTransform],
+      Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform],
       Dependency[firrtl.transforms.FlattenRegUpdate]
     )
 

src/main/scala/firrtl/passes/VerilogPrep.scala

@@ -29,7 +29,7 @@ object VerilogPrep extends Pass {
       Dependency[firrtl.transforms.ReplaceTruncatingArithmetic],
       Dependency[firrtl.transforms.InlineBitExtractionsTransform],
       Dependency[firrtl.transforms.InlineAcrossCastsTransform],
-      Dependency[firrtl.transforms.LegalizeClocksTransform],
+      Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform],
       Dependency[firrtl.transforms.FlattenRegUpdate],
       Dependency(passes.VerilogModulusCleanup),
       Dependency[firrtl.transforms.VerilogRename]

src/main/scala/firrtl/passes/ZeroWidth.scala

@@ -204,6 +204,6 @@ object ZeroWidth extends Transform with DependencyAPIMigration {
     val renames = MutableRenameMap()
     renames.setCircuit(c.main)
     val result = c.copy(modules = c.modules.map(onModule(renames)))
-    CircuitState(result, outputForm, state.annotations, Some(renames))
+    state.copy(circuit = result, renames = Some(renames))
   }
 }

src/main/scala/firrtl/stage/Forms.scala

@@ -112,7 +112,7 @@ object Forms {
         Dependency[firrtl.transforms.ReplaceTruncatingArithmetic],
         Dependency[firrtl.transforms.InlineBitExtractionsTransform],
         Dependency[firrtl.transforms.InlineAcrossCastsTransform],
-        Dependency[firrtl.transforms.LegalizeClocksTransform],
+        Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform],
         Dependency[firrtl.transforms.FlattenRegUpdate],
         Dependency(passes.VerilogModulusCleanup),
         Dependency[firrtl.transforms.VerilogRename],

src/main/scala/firrtl/transforms/FlattenRegUpdate.scala

@@ -171,7 +171,7 @@ class FlattenRegUpdate extends Transform with DependencyAPIMigration {
       Dependency[ReplaceTruncatingArithmetic],
       Dependency[InlineBitExtractionsTransform],
       Dependency[InlineAcrossCastsTransform],
-      Dependency[LegalizeClocksTransform]
+      Dependency[LegalizeClocksAndAsyncResetsTransform]
     )
 
   override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized

src/main/scala/firrtl/transforms/GroupComponents.scala

@@ -336,13 +336,6 @@ class GroupComponents extends Transform with DependencyAPIMigration {
     }
     def onStmt(stmt: Statement): Unit = stmt match {
       case w: WDefInstance =>
-      case h: IsDeclaration =>
-        bidirGraph.addVertex(h.name)
-        h.map(onExpr(WRef(h.name)))
-      case Attach(_, exprs) => // Add edge between each expression
-        exprs.tail.map(onExpr(getWRef(exprs.head)))
-      case Connect(_, loc, expr) =>
-        onExpr(getWRef(loc))(expr)
       case q @ Stop(_, _, clk, en) =>
         val simName = simNamespace.newTemp
         simulations(simName) = q
@@ -351,6 +344,13 @@ class GroupComponents extends Transform with DependencyAPIMigration {
         val simName = simNamespace.newTemp
         simulations(simName) = q
         (args :+ clk :+ en).map(onExpr(WRef(simName)))
+      case h: IsDeclaration =>
+        bidirGraph.addVertex(h.name)
+        h.map(onExpr(WRef(h.name)))
+      case Attach(_, exprs) => // Add edge between each expression
+        exprs.tail.map(onExpr(getWRef(exprs.head)))
+      case Connect(_, loc, expr) =>
+        onExpr(getWRef(loc))(expr)
       case Block(stmts) => stmts.foreach(onStmt)
       case ignore @ (_: IsInvalid | EmptyStmt) => // do nothing
       case other => throw new Exception(s"Unexpected Statement $other")

src/main/scala/firrtl/transforms/InlineAcrossCastsTransform.scala

@@ -97,7 +97,7 @@ class InlineAcrossCastsTransform extends Transform with DependencyAPIMigration {
   override def optionalPrerequisiteOf = Seq.empty
 
   override def invalidates(a: Transform): Boolean = a match {
-    case _: LegalizeClocksTransform => true
+    case _: LegalizeClocksAndAsyncResetsTransform => true
     case _ => false
   }
 

src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala

@@ -38,7 +38,7 @@ class VerilogRename extends RemoveKeywordCollisions(v_keywords) {
       Dependency[ReplaceTruncatingArithmetic],
       Dependency[InlineBitExtractionsTransform],
       Dependency[InlineAcrossCastsTransform],
-      Dependency[LegalizeClocksTransform],
+      Dependency[LegalizeClocksAndAsyncResetsTransform],
       Dependency[FlattenRegUpdate],
       Dependency(passes.VerilogModulusCleanup)
     )

src/main/scala/firrtl/transforms/RemoveReset.scala

@@ -50,6 +50,7 @@ object RemoveReset extends Transform with DependencyAPIMigration {
 
   private def onModule(m: DefModule, isPreset: String => Boolean): DefModule = {
     val resets = mutable.HashMap.empty[String, Reset]
+    val asyncResets = mutable.HashMap.empty[String, Reset]
     val invalids = computeInvalids(m)
     def onStmt(stmt: Statement): Statement = {
       stmt match {
@@ -77,12 +78,21 @@ object RemoveReset extends Transform with DependencyAPIMigration {
           // Add register reset to map
           resets(rname) = Reset(reset, init, info)
           reg.copy(reset = Utils.zero, init = WRef(reg))
+        case reg @ DefRegister(info, rname, _, _, reset, init) if reset.tpe == AsyncResetType =>
+          asyncResets(rname) = Reset(reset, init, info)
+          reg
         case Connect(info, ref @ WRef(rname, _, RegKind, _), expr) if resets.contains(rname) =>
           val reset = resets(rname)
           val muxType = Utils.mux_type_and_widths(reset.value, expr)
           // Use reg source locator for mux enable and true value since that's where they're defined
           val infox = MultiInfo(reset.info, reset.info, info)
           Connect(infox, ref, Mux(reset.cond, reset.value, expr, muxType))
+        case Connect(info, ref @ WRef(rname, _, RegKind, _), expr) if asyncResets.contains(rname) =>
+          val reset = asyncResets(rname)
+          // The `muxType` for async always blocks is located in [[VerilogEmitter.VerilogRender.regUpdate]]:
+          // addUpdate(info, Mux(reset, tv, fv, mux_type_and_widths(tv, fv)), Seq.empty)
+          val infox = MultiInfo(reset.info, reset.info, info)
+          Connect(infox, ref, expr)
         case other => other.map(onStmt)
       }
     }

src/main/scala/logger/LoggerOptions.scala

@@ -32,7 +32,7 @@ class LoggerOptions private[logger] (
   }
 
   /** Return the name of the log file, defaults to `a.log` if unspecified */
-  def getLogFileName(): Option[String] = if (!logToFile()) None else logFileName.orElse(Some("a.log"))
+  def getLogFileName(): Option[String] = logFileName.orElse(Some("a.log"))
 
   /** True if a [[Logger]] should be writing to a file */
   @deprecated("logToFile was removed, use logFileName.nonEmpty", "FIRRTL 1.2")

src/test/scala/firrtl/backends/experimental/smt/FirrtlExpressionSemanticsSpec.scala

@@ -278,4 +278,35 @@ class FirrtlExpressionSemanticsSpec extends AnyFlatSpec {
     assert(primop(false, "tail", 4, List(5), List(1)) == "i0[3:0]")
     assert(primop(false, "tail", 2, List(5), List(3)) == "i0[1:0]")
   }
+
+  private def literalSource(resTpe: String, lit: String) =
+    s"""circuit m:
+       |  module m:
+       |    output res: $resTpe
+       |    res <= $lit
+       |
+       |""".stripMargin
+  private def literalExpr(resTpe: String, lit: String) = {
+    val src = literalSource(resTpe, lit)
+    val sys = SMTBackendHelpers.toSys(src, modelUndef = true)
+    sys.signals.last.e.toString
+  }
+
+  private def uIntLit(lit: String) = literalExpr("UInt", lit)
+  it should "correctly translate unsigned integer literals" in {
+    assert(uIntLit("UInt(5)") == "3'b101")
+    assert(uIntLit("UInt<4>(5)") == "4'b101")
+    assert(uIntLit("UInt(0)") == "1'b0")
+  }
+
+  private def sIntLit(lit: String) = literalExpr("SInt", lit)
+  it should "correctly translate signed integer literals" in {
+    assert(sIntLit("SInt(5)") == "4'b101")
+    assert(sIntLit("SInt<4>(5)") == "4'b101")
+    assert(sIntLit("SInt(0)") == "1'b0")
+    assert(sIntLit("SInt(-1)") == "1'b1")
+    assert(sIntLit("SInt(-2)") == "2'b10")
+    assert(sIntLit("SInt(-5)") == "4'b1011")
+    assert(sIntLit("SInt<4>(-5)") == "4'b1011")
+  }
 }

src/test/scala/firrtlTests/VerilogEmitterTests.scala

@@ -717,6 +717,22 @@ class VerilogEmitterSpec extends FirrtlFlatSpec {
     result should containLine("assign z = x == y;")
   }
 
+  it should "show line numbers for AsyncReset regUpdate" in {
+    val result = compileBody(
+      """input clock : Clock
+        |input reset : AsyncReset
+        |output io : { flip in : UInt<1>, out : UInt<1>}
+        |
+        |reg valid : UInt<1>, clock with :
+        |  reset => (reset, UInt<1>("h0")) @[Playground.scala 11:22]
+        |valid <= io.in @[Playground.scala 12:9]
+        |io.out <= valid @[Playground.scala 13:10]""".stripMargin
+    )
+    result should containLine("if (reset) begin // @[Playground.scala 11:22]")
+    result should containLine("valid <= 1'h0; // @[Playground.scala 11:22]")
+    result should containLine("valid <= io_in; // @[Playground.scala 12:9]")
+  }
+
   it should "subtract positive literals instead of adding negative literals" in {
     val compiler = new VerilogCompiler
     val result = compileBody(