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Add --dont-fold option to disable folding specific prim ops #2040
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seldridge
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Add --dont-fold option to disable folding prim ops
Add --dont-fold option to disable folding specific prim ops
Jan 16, 2021
jackkoenig
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Some pretty big nits, but otherwise this looks good!
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This adds a --dont-fold options (backed by a DisableFold annotation) that lets a user specify primitive operations which should never be folded. This feature lets a user disable certain folds which may be allowable in FIRRTL (or by any sane synthesis tool), but due to inane Verilog language design causes formal equivalence tools to fail due to the fold. Add a test that a user can disable `a / a -> 1` with a DisableFold(PrimOps.Div) annotation. Signed-off-by: Schuyler Eldridge <[email protected]>
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This adds a --dont-fold options (backed by a DisableFold annotation) that lets a user specify primitive operations which should never be folded. This feature lets a user disable certain folds which may be allowable in FIRRTL (or by any sane synthesis tool), but due to inane Verilog language design causes formal equivalence tools to fail due to the fold. Add a test that a user can disable `a / a -> 1` with a DisableFold(PrimOps.Div) annotation. Signed-off-by: Schuyler Eldridge <[email protected]> (cherry picked from commit 698a9dc)
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This adds a --dont-fold options (backed by a DisableFold annotation) that lets a user specify primitive operations which should never be folded. This feature lets a user disable certain folds which may be allowable in FIRRTL (or by any sane synthesis tool), but due to inane Verilog language design causes formal equivalence tools to fail due to the fold. Add a test that a user can disable `a / a -> 1` with a DisableFold(PrimOps.Div) annotation. Signed-off-by: Schuyler Eldridge <[email protected]> (cherry picked from commit 698a9dc) Co-authored-by: Schuyler Eldridge <[email protected]>
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This adds a --dont-fold options (backed by a DisableFold annotation)
that lets a user specify primitive operations which should never be
folded. This feature lets a user disable certain folds which may be
allowable in FIRRTL (or by any sane synthesis tool), but due to inane
Verilog language design causes formal equivalence tools to fail due to
the fold.
Add a test that a user can disable
a / a -> 1
with aDisableFold(PrimOps.Div) annotation.
Fixes #2029.
Example Usage
The following circuit:
When normally compiled will have
div(a, a)
legally optimized to1
by taking advantage of the fact that division by zero is undefined in the FIRRTL spec (and arguably is implicitly undefined for synthesis in Verilog...):If a user disables folding of division:
The user gets an
a / a
in the output:Contributor Checklist
Type of Improvement
API Impact
This is a pure command line / annotation API addition.
Backend Code Generation Impact
None by default. A user can elect to change the backend code generation with the new
--dont-fold
option.Desired Merge Strategy
Release Notes
--dont-fold
option to disable folding a specific primopReviewer Checklist (only modified by reviewer)
Please Merge
?