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Add -fpga flag to enable FPGA-oriented compilation strategies (currently for memories)#2111

Merged

albert-magyar merged 10 commits intomasterfrom fpga-backend

Apr 5, 2021

+456-68

Commits on Apr 5, 2021

Specify that SimplifyMems invalidates InferTypes
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Allow direct emission of sync-read memories to Verilog
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Optionally allow simple SyncReadMems to pass through VerilogMemDelays
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Add SetDefaultReadUnderWrite transform
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Allow InferReadWrite to combine shared-address R/W ports when appropriate
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Add tests for same-address readwrite inference
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Add SeparateWriteClocks to ensure one mem write per Verilog process
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Add --target:fpga flag to prioritize FPGA-friendly compilation
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Add test for SeparateWriteClocks
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Establish a fixed relative order for FPGA-backed passes + reflect in ScalaDoc
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