Add memory initialization options for synthesis

[carlosedp]

This PR adds options for memory initialization inside or outside the
ifndef SYNTHESIS block.

Fixes #2114.

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you update the FIRRTL spec to include every new feature/behavior?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
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• Did you specify the code generation impact?
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Type of Improvement

• new feature/API

API Impact

This new feature adds memory initialization options for having the readmem blocks inside or outside the existing ifndef SYNTHESIS.

In the future, this parameter can be used by the -target:fpga PR (#2111) that is in development.

Backend Code Generation Impact

This changes the generated Verilog code based on the parameters:

If using MemoryNoSynthInit (current default):

...
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
  `endif // RANDOMIZE
  $readmemh("sample.hex", mem);
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule

If using MemorySynthInit:

initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
  initial begin
    $readmemh("sample.hex", mem);
  end
endmodule

Desired Merge Strategy

• Squash: The PR will be squashed and merged (choose this if you have no preference.

Release Notes

This PR adds two annotations to determine how readmem statements are generated in Verilog code.
By default, it is placed inside the ifndef SYNTHESIS block which gets ignored by some FPGA tools.
One can add either MemorySynthInit or MemoryNoSynthInit (which is the default if not defined) annotation to change the behaviour and have the readmem outside this ifndef block.

In the future, MemorySynthInit could be set as default for FPGA targets (-target:FPGA).

TBD

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[carlosedp]

I'd like some feedback on this approach and if it's the correct way to do it.

I successfully got the results by changing the parameter on def initValue: MemoryInitEmissionValue = MemoryNoSynthInit but don't know how to make it change based on different generation parameters (like the one currently in dev in PR #2111.

Also would be great to have a way to use this until the FPGA target is done.

I thought about something like an annotation:

  annotate(new ChiselAnnotation {
    override def toFirrtl =
      firrtl.MemoryInitEmissionOption = firrtl.MemorySynthInit
  })

But can't figure out how :)

[carlosedp]

I think is is much cleaner and allows defining the behaviour by using an annotation in the Chisel code.

  annotate(new ChiselAnnotation {
    override def toFirrtl =
      firrtl.annotations.MemorySynthInit
      // or
      // firrtl.annotations.MemoryNoSynthInit
  })

  val mem = SyncReadMem(words, UInt(bitWidth.W))
  if (memoryFile.trim().nonEmpty) {
    println(s"  Load memory file: " + memoryFile)
    loadMemoryFromFileInline(mem, memoryFile)
  }

[carlosedp]

Also I tested that the MemorySynthInit/MemoryNoSynthInit annotation doesn't need to be in the memory module itself. It can be in the Topmodule for example and works fine.

Changes were made