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Fix dshl zero-width shift behavior #2339

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merged 2 commits into from
Aug 26, 2021
Merged

Fix dshl zero-width shift behavior #2339

merged 2 commits into from
Aug 26, 2021

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@seldridge seldridge commented Aug 26, 2021 •
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Add a special case for dshl handling in the ZeroWidths pass. If one
expression is shifted by a second, zero-width expression, just return
the first expression. This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.

Signed-off-by: Schuyler Eldridge [email protected]

Fixes llvm/circt#1643.

Contributor Checklist

  • [n/a] Did you add Scaladoc to every public function/method?
  • [n/a] Did you update the FIRRTL spec to include every new feature/behavior?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
  • Did you specify the type of improvement?
  • Did you state the API impact?
  • Did you specify the code generation impact?
  • Did you request a desired merge strategy?
  • Did you add text to be included in the Release Notes for this change?

Type of Improvement

  • bug fix

API Impact

None.

Backend Code Generation Impact

Change behavior of ZeroWidths to treat dshl(a, 0-width) as a. This changes the code generation for some circuits.

Desired Merge Strategy

  • Squash: The PR will be squashed and merged (choose this if you have no preference.

Release Notes

Reviewer Checklist (only modified by reviewer)

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  • Did you mark the proper milestone (1.2.x, 1.3.0, 1.4.0) ?
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@seldridge
Fix dshl zero-width shift behavior
284484b 
Add a special case for dshl handling in the ZeroWidths pass.  If one
expression is shifted by a second, zero-width expression, just return
the first expression.  This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.

Signed-off-by: Schuyler Eldridge <[email protected]>
@seldridge seldridge mentioned this pull request Aug 26, 2021
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@jackkoenig jackkoenig added this to the 1.3.x milestone Aug 26, 2021
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jackkoenig approved these changes Aug 26, 2021
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LGTM, I've marked this 1.3.x per our new policy of backporting bugfixes 2 versions by default.

@seldridge seldridge added the Please Merge Accepted PRs that are ready to be merged. Useful when waiting on CI. label Aug 26, 2021
@mergify mergify bot merged commit cc80c63 into master Aug 26, 2021
mergify bot pushed a commit that referenced this pull request Aug 26, 2021
@seldridge
Fix dshl zero-width shift behavior (#2339)
796dfe4 
* Fix dshl zero-width shift behavior

Add a special case for dshl handling in the ZeroWidths pass.  If one
expression is shifted by a second, zero-width expression, just return
the first expression.  This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.

Signed-off-by: Schuyler Eldridge <[email protected]>

* fixup! Fix dshl zero-width shift behavior

(cherry picked from commit cc80c63)

# Conflicts:
#	src/main/scala/firrtl/passes/ZeroWidth.scala
@mergify mergify bot mentioned this pull request Aug 26, 2021
Merged
mergify bot pushed a commit that referenced this pull request Aug 26, 2021
@seldridge
Fix dshl zero-width shift behavior (#2339)
dee5e9f 
* Fix dshl zero-width shift behavior

Add a special case for dshl handling in the ZeroWidths pass.  If one
expression is shifted by a second, zero-width expression, just return
the first expression.  This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.

Signed-off-by: Schuyler Eldridge <[email protected]>

* fixup! Fix dshl zero-width shift behavior

(cherry picked from commit cc80c63)
@mergify mergify bot mentioned this pull request Aug 26, 2021
Merged
@mergify mergify bot added the Backported This PR has been backported to marked stable branch label Aug 26, 2021
mergify bot added a commit that referenced this pull request Aug 26, 2021
@mergify @seldridge
Fix dshl zero-width shift behavior (#2339) (#2341)
fe5a56e 
* Fix dshl zero-width shift behavior

Add a special case for dshl handling in the ZeroWidths pass.  If one
expression is shifted by a second, zero-width expression, just return
the first expression.  This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.

Signed-off-by: Schuyler Eldridge <[email protected]>

* fixup! Fix dshl zero-width shift behavior

(cherry picked from commit cc80c63)

Co-authored-by: Schuyler Eldridge <[email protected]>
seldridge added a commit that referenced this pull request Aug 26, 2021
@seldridge
fixup! Fix dshl zero-width shift behavior (#2339)
652ddcd
mergify bot added a commit that referenced this pull request Aug 26, 2021
@mergify @seldridge
Fix dshl zero-width shift behavior (backport #2339) (#2340)
b1a968b 
* Fix dshl zero-width shift behavior (#2339)

* Fix dshl zero-width shift behavior

Add a special case for dshl handling in the ZeroWidths pass.  If one
expression is shifted by a second, zero-width expression, just return
the first expression.  This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.

Signed-off-by: Schuyler Eldridge <[email protected]>

* fixup! Fix dshl zero-width shift behavior

(cherry picked from commit cc80c63)

# Conflicts:
#	src/main/scala/firrtl/passes/ZeroWidth.scala

* fixup! Fix dshl zero-width shift behavior (#2339)

Co-authored-by: Schuyler Eldridge <[email protected]>
@seldridge seldridge deleted the dev/seldridge/circt-1643 branch August 26, 2021 18:38
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[FIRRTL] (dshl) long mismatch
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