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busmux_0.v
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busmux_0.v
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// Copyright (C) 2023 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.
// PROGRAM "Quartus Prime"
// VERSION "Version 22.1std.1 Build 917 02/14/2023 SC Standard Edition"
// CREATED "Thu Apr 18 13:07:47 2024"
module busmux_0(sel,dataa,datab,result);
input sel;
input [0:0] dataa;
input [0:0] datab;
output [0:0] result;
busmux lpm_instance(.sel(sel),.dataa(dataa),.datab(datab),.result(result));
defparam lpm_instance.width = 1;
endmodule