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delayCounter13bit_inst.v
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delayCounter13bit_inst.v
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// Copyright (C) 2023 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.
// Generated by Quartus Prime Version 22.1 (Build Build 917 02/14/2023)
// Created on Tue Apr 30 02:07:52 2024
delayCounter13bit delayCounter13bit_inst
(
.Enable(Enable_sig) , // input Enable_sig
.Clock3(Clock3_sig) , // input Clock3_sig
.CLRN(CLRN_sig) , // input CLRN_sig
.out(out_sig) // output [12:0] out_sig
);