riscv64: Avoid F and V instruction generation #455

	name: Rust Hypervisor Firmware Build
	on: [pull_request, create]

	env:
	RUSTFLAGS: "-D warnings"

	jobs:
	build:
	if: github.event_name == 'pull_request'
	name: Build
	runs-on: ubuntu-20.04
	strategy:
	fail-fast: false
	matrix:
	include:
	- target: x86_64-unknown-none.json
	tests: true
	- target: aarch64-unknown-none.json
	tests: false
	- target: riscv64gcv-unknown-none-elf.json
	tests: false
	steps:
	- name: Code checkout
	uses: actions/checkout@v2
	with:
	fetch-depth: 0
	- name: Install Rust toolchain
	uses: dtolnay/rust-toolchain@stable
	- name: Install Rust components
	run: rustup component add rust-src clippy rustfmt
	- name: Build (debug)
	run: cargo build --target ${{ matrix.target }} -Zbuild-std=core,alloc -Zbuild-std-features=compiler-builtins-mem
	- name: Build (release)
	run: cargo build --release --target ${{ matrix.target }} -Zbuild-std=core,alloc -Zbuild-std-features=compiler-builtins-mem
	- name: Clippy (default)
	run: cargo clippy --target ${{ matrix.target }} -Zbuild-std=core,alloc
	- name: Clippy (all targets, all features)
	run: cargo clippy --all-targets --all-features
	- name: Formatting
	run: cargo fmt --all -- --check
	- if: ${{ matrix.tests }}
	name: Unit tests
	run: \|
	sudo apt-get install -y mtools
	bash scripts/run_unit_tests.sh

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