CachePadded: Use 32-byte alignment on riscv32/sparc/hexagon, 16-byte alignment on m68k

[taiki-e]

• riscv32 is assumed not to exceed the cache line size of riscv64.
• sparc, hexagon, and m68k's cache line sizes are from Linux kernel's __cacheline_aligned (SMP_CACHE_BYTES, or L1_CACHE_BYTES if SMP_CACHE_BYTES is not set).

[taiki-e]

Linux kernel's __cacheline_aligned (SMP_CACHE_BYTES, or L1_CACHE_BYTES if SMP_CACHE_BYTES is not set)

I'm aware of the values defined by the Linux kernel and those defined by us are different for some architectures (e.g., aarch64, riscv ¹), but for now, I have preferred the source we are currently referring to.

Footnotes

1. As far as I know, the actual cache line size for both aarch64 and riscv is implementation dependent (like other architectures such as x86, arm, powerpc, mips, xtensa, loongarch) ↩

[taiki-e]

bors r+

[bors]

Build succeeded:

• ci
• test (aarch64-apple-darwin)
• test (aarch64-unknown-linux-gnu)
• test (x86_64-apple-darwin)