-
Notifications
You must be signed in to change notification settings - Fork 1.4k
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Adds column number to the verilator verilog linter
Since version 4.032 (04/2020) verilator linter messages also contain the column number, and look like: %Error: /tmp/test.sv:3:1: syntax error, unexpected endmodule, expecting ';' To stay compatible with old versions of the tool, the column number is optional in the researched pattern regular expression. See commit: verilator/verilator@81c6599
- Loading branch information
1 parent
198361b
commit 00eee55
Showing
2 changed files
with
66 additions
and
9 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,48 @@ | ||
Before: | ||
runtime ale_linters/verilog/verilator.vim | ||
|
||
After: | ||
call ale#linter#Reset() | ||
|
||
|
||
Execute (The verilator handler should parse legacy messages with only line numbers): | ||
AssertEqual | ||
\ [ | ||
\ { | ||
\ 'lnum': 3, | ||
\ 'type': 'E', | ||
\ 'text': 'syntax error, unexpected IDENTIFIER' | ||
\ }, | ||
\ { | ||
\ 'lnum': 10, | ||
\ 'type': 'W', | ||
\ 'text': 'Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).' | ||
\ }, | ||
\ ], | ||
\ ale_linters#verilog#verilator#Handle(bufnr(''), [ | ||
\ '%Error: foo_verilator_linted.v:3: syntax error, unexpected IDENTIFIER', | ||
\ '%Warning-BLKSEQ: bar_verilator_linted.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).', | ||
\ ]) | ||
|
||
|
||
Execute (The verilator handler should parse new format messages with line and column numbers): | ||
AssertEqual | ||
\ [ | ||
\ { | ||
\ 'lnum': 3, | ||
\ 'col' : 1, | ||
\ 'type': 'E', | ||
\ 'text': 'syntax error, unexpected endmodule, expecting ;' | ||
\ }, | ||
\ { | ||
\ 'lnum': 4, | ||
\ 'col' : 6, | ||
\ 'type': 'W', | ||
\ 'text': 'Signal is not used: r' | ||
\ }, | ||
\ ], | ||
\ ale_linters#verilog#verilator#Handle(bufnr(''), [ | ||
\ '%Error: bar_verilator_linted.v:3:1: syntax error, unexpected endmodule, expecting ;', | ||
\ '%Warning-UNUSED: foo_verilator_linted.v:4:6: Signal is not used: r', | ||
\ ]) | ||
|