move more things to init

esp-rs · Sep 5, 2024 · befe0e0 · befe0e0
1 parent e785ac3
commit befe0e0
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Showing 11 changed files with 29 additions and 115 deletions.
diff --git a/esp-hal-embassy/src/time_driver.rs b/esp-hal-embassy/src/time_driver.rs
@@ -5,7 +5,7 @@ use embassy_time_driver::{AlarmHandle, Driver};
 use esp_hal::{
     interrupt::{InterruptHandler, Priority},
     prelude::*,
-    time::current_time,
+    time::uptime,
     timer::{ErasedTimer, OneShotTimer},
 };
 
@@ -119,7 +119,7 @@ impl EmbassyTimer {
     }
 
     fn arm(timer: &mut Timer, timestamp: u64) {
-        let now = current_time().duration_since_epoch();
+        let now = uptime().duration_since_epoch();
         let ts = timestamp.micros();
         // if the TS is already in the past make the timer fire immediately
         let timeout = if ts > now { ts - now } else { 0.micros() };
@@ -130,7 +130,7 @@ impl EmbassyTimer {
 
 impl Driver for EmbassyTimer {
     fn now(&self) -> u64 {
-        current_time().ticks()
+        uptime().ticks()
     }
 
     unsafe fn allocate_alarm(&self) -> Option<AlarmHandle> {

diff --git a/esp-hal/src/delay.rs b/esp-hal/src/delay.rs
@@ -31,7 +31,7 @@
 //! [DelayMs]: embedded_hal_02::blocking::delay::DelayMs
 //! [DelayUs]: embedded_hal_02::blocking::delay::DelayUs
 //! [embedded-hal]: https://docs.rs/embedded-hal/1.0.0/embedded_hal/delay/index.html
-//! [current_time]: crate::time::current_time
+//! [current_time]: crate::time::uptime
 
 pub use fugit::MicrosDurationU64;
 
@@ -75,7 +75,7 @@ impl Delay {
 
     /// Delay for the specified time
     pub fn delay(&self, delay: MicrosDurationU64) {
-        let start = crate::time::current_time();
+        let start = crate::time::uptime();
 
         while elapsed_since(start) < delay {}
     }
@@ -101,7 +101,7 @@ impl Delay {
 }
 
 fn elapsed_since(start: fugit::Instant<u64, 1, 1_000_000>) -> MicrosDurationU64 {
-    let now = crate::time::current_time();
+    let now = crate::time::uptime();
 
     if start.ticks() <= now.ticks() {
         now - start

diff --git a/esp-hal/src/lib.rs b/esp-hal/src/lib.rs
@@ -734,9 +734,27 @@ pub struct Config {
 ///
 /// This function sets up the CPU clock and returns the peripherals and clocks.
 pub fn init(config: Config) -> Peripherals {
+    use self::peripherals::*;
     let peripherals = Peripherals::take();
 
     Clocks::init(config.cpu_clock);
 
+    #[cfg(xtensa)]
+    crate::interrupt::setup_interrupts();
+    #[cfg(esp32)]
+    crate::time::time_init();
+
+    // RTC domain must be enabled before we try to disable
+    let mut rtc = crate::rtc_cntl::Rtc::new(unsafe { LPWR::steal() });
+    #[cfg(not(any(esp32, esp32s2)))]
+    rtc.swd.disable();
+    rtc.rwdt.disable();
+
+    unsafe {
+        crate::timer::timg::Wdt::<TIMG0, crate::Blocking>::set_wdt_enabled(false);
+        #[cfg(timg1)]
+        crate::timer::timg::Wdt::<TIMG1, crate::Blocking>::set_wdt_enabled(false);
+    }
+
     peripherals
 }
diff --git a/esp-hal/src/soc/esp32/mod.rs b/esp-hal/src/soc/esp32/mod.rs
@@ -7,11 +7,7 @@
 
 use core::ptr::addr_of_mut;
 
-use self::peripherals::{LPWR, TIMG0, TIMG1};
-use crate::{
-    rtc_cntl::{Rtc, SocResetReason},
-    timer::timg::Wdt,
-};
+use crate::rtc_cntl::SocResetReason;
 
 pub mod cpu_control;
 pub mod efuse;
@@ -111,9 +107,6 @@ pub unsafe extern "C" fn ESP32Reset() -> ! {
         stack_chk_guard.write_volatile(0xdeadbabe);
     }
 
-    crate::interrupt::setup_interrupts();
-    crate::time::time_init();
-
     // continue with default reset handler
     xtensa_lx_rt::Reset();
 }
@@ -126,13 +119,3 @@ pub unsafe extern "C" fn ESP32Reset() -> ! {
 pub extern "Rust" fn __init_data() -> bool {
     false
 }
-
-#[export_name = "__post_init"]
-unsafe fn post_init() {
-    // RTC domain must be enabled before we try to disable
-    let mut rtc = Rtc::new(LPWR::steal());
-    rtc.rwdt.disable();
-
-    Wdt::<TIMG0, crate::Blocking>::set_wdt_enabled(false);
-    Wdt::<TIMG1, crate::Blocking>::set_wdt_enabled(false);
-}
diff --git a/esp-hal/src/soc/esp32c2/mod.rs b/esp-hal/src/soc/esp32c2/mod.rs
@@ -5,9 +5,6 @@
 //! The `SOC` module provides access, functions and structures that are useful
 //! for interacting with various system-related peripherals on `ESP32-C2` chip.
 
-use self::peripherals::{LPWR, TIMG0};
-use crate::{rtc_cntl::Rtc, timer::timg::Wdt};
-
 pub mod efuse;
 pub mod gpio;
 pub mod peripherals;
@@ -38,13 +35,3 @@ pub(crate) mod constants {
     /// RC FAST Clock value (Hertz).
     pub const RC_FAST_CLK: fugit::HertzU32 = fugit::HertzU32::kHz(17500);
 }
-
-#[export_name = "__post_init"]
-unsafe fn post_init() {
-    // RTC domain must be enabled before we try to disable
-    let mut rtc = Rtc::new(LPWR::steal());
-    rtc.swd.disable();
-    rtc.rwdt.disable();
-
-    Wdt::<TIMG0, crate::Blocking>::set_wdt_enabled(false);
-}
diff --git a/esp-hal/src/soc/esp32c3/mod.rs b/esp-hal/src/soc/esp32c3/mod.rs
@@ -9,9 +9,6 @@
 //!    * I2S_SCLK: 160_000_000 - I2S clock frequency
 //!    * I2S_DEFAULT_CLK_SRC: 2 - I2S clock source
 
-use self::peripherals::{LPWR, TIMG0, TIMG1};
-use crate::{rtc_cntl::Rtc, timer::timg::Wdt};
-
 pub mod efuse;
 pub mod gpio;
 pub mod peripherals;
@@ -56,14 +53,3 @@ pub(crate) mod constants {
     /// RC FAST Clock value (Hertz).
     pub const RC_FAST_CLK: fugit::HertzU32 = fugit::HertzU32::kHz(17500);
 }
-
-#[export_name = "__post_init"]
-unsafe fn post_init() {
-    // RTC domain must be enabled before we try to disable
-    let mut rtc = Rtc::new(LPWR::steal());
-    rtc.swd.disable();
-    rtc.rwdt.disable();
-
-    Wdt::<TIMG0, crate::Blocking>::set_wdt_enabled(false);
-    Wdt::<TIMG1, crate::Blocking>::set_wdt_enabled(false);
-}
diff --git a/esp-hal/src/soc/esp32c6/mod.rs b/esp-hal/src/soc/esp32c6/mod.rs
@@ -10,9 +10,6 @@
 //!    * I2S_DEFAULT_CLK_SRC: 2 - I2S clock source
 //!    * I2S_SCLK: 160_000_000 - I2S clock frequency
 
-use self::peripherals::{LPWR, TIMG0, TIMG1};
-use crate::{rtc_cntl::Rtc, timer::timg::Wdt};
-
 pub mod efuse;
 pub mod gpio;
 pub mod lp_core;
@@ -64,14 +61,3 @@ pub(crate) mod constants {
     /// RC FAST Clock value (Hertz).
     pub const RC_FAST_CLK: fugit::HertzU32 = fugit::HertzU32::kHz(17_500);
 }
-
-#[export_name = "__post_init"]
-unsafe fn post_init() {
-    // RTC domain must be enabled before we try to disable
-    let mut rtc = Rtc::new(LPWR::steal());
-    rtc.swd.disable();
-    rtc.rwdt.disable();
-
-    Wdt::<TIMG0, crate::Blocking>::set_wdt_enabled(false);
-    Wdt::<TIMG1, crate::Blocking>::set_wdt_enabled(false);
-}
diff --git a/esp-hal/src/soc/esp32h2/mod.rs b/esp-hal/src/soc/esp32h2/mod.rs
@@ -10,9 +10,6 @@
 //!    * I2S_DEFAULT_CLK_SRC: 1 - I2S clock source
 //!    * I2S_SCLK: 96_000_000 - I2S clock frequency
 
-use self::peripherals::{LPWR, TIMG0, TIMG1};
-use crate::{rtc_cntl::Rtc, timer::timg::Wdt};
-
 pub mod efuse;
 pub mod gpio;
 pub mod peripherals;
@@ -64,14 +61,3 @@ pub(crate) mod constants {
     /// RC FAST Clock value (Hertz).
     pub const RC_FAST_CLK: fugit::HertzU32 = fugit::HertzU32::kHz(17500);
 }
-
-#[export_name = "__post_init"]
-unsafe fn post_init() {
-    // RTC domain must be enabled before we try to disable
-    let mut rtc = Rtc::new(LPWR::steal());
-    rtc.swd.disable();
-    rtc.rwdt.disable();
-
-    Wdt::<TIMG0, crate::Blocking>::set_wdt_enabled(false);
-    Wdt::<TIMG1, crate::Blocking>::set_wdt_enabled(false);
-}
diff --git a/esp-hal/src/soc/esp32s2/mod.rs b/esp-hal/src/soc/esp32s2/mod.rs
@@ -11,11 +11,7 @@
 
 use core::ptr::addr_of_mut;
 
-use self::peripherals::{LPWR, TIMG0, TIMG1};
-use crate::{
-    rtc_cntl::{Rtc, SocResetReason},
-    timer::timg::Wdt,
-};
+use crate::rtc_cntl::SocResetReason;
 
 pub mod efuse;
 pub mod gpio;
@@ -116,8 +112,6 @@ pub unsafe extern "C" fn ESP32Reset() -> ! {
         stack_chk_guard.write_volatile(0xdeadbabe);
     }
 
-    crate::interrupt::setup_interrupts();
-
     // continue with default reset handler
     xtensa_lx_rt::Reset();
 }
@@ -130,13 +124,3 @@ pub unsafe extern "C" fn ESP32Reset() -> ! {
 pub extern "Rust" fn __init_data() -> bool {
     false
 }
-
-#[export_name = "__post_init"]
-unsafe fn post_init() {
-    // RTC domain must be enabled before we try to disable
-    let mut rtc = Rtc::new(LPWR::steal());
-    rtc.rwdt.disable();
-
-    Wdt::<TIMG0, crate::Blocking>::set_wdt_enabled(false);
-    Wdt::<TIMG1, crate::Blocking>::set_wdt_enabled(false);
-}
diff --git a/esp-hal/src/soc/esp32s3/mod.rs b/esp-hal/src/soc/esp32s3/mod.rs
@@ -11,11 +11,7 @@
 
 use core::ptr::addr_of_mut;
 
-use self::peripherals::{LPWR, TIMG0, TIMG1};
-use crate::{
-    rtc_cntl::{Rtc, SocResetReason},
-    timer::timg::Wdt,
-};
+use crate::rtc_cntl::SocResetReason;
 
 pub mod cpu_control;
 pub mod efuse;
@@ -155,8 +151,6 @@ pub unsafe extern "C" fn ESP32Reset() -> ! {
         stack_chk_guard.write_volatile(0xdeadbabe);
     }
 
-    crate::interrupt::setup_interrupts();
-
     // continue with default reset handler
     xtensa_lx_rt::Reset();
 }
@@ -170,16 +164,6 @@ pub extern "Rust" fn __init_data() -> bool {
     false
 }
 
-#[export_name = "__post_init"]
-unsafe fn post_init() {
-    // RTC domain must be enabled before we try to disable
-    let mut rtc = Rtc::new(LPWR::steal());
-    rtc.rwdt.disable();
-
-    Wdt::<TIMG0, crate::Blocking>::set_wdt_enabled(false);
-    Wdt::<TIMG1, crate::Blocking>::set_wdt_enabled(false);
-}
-
 /// Write back a specific range of data in the cache.
 #[doc(hidden)]
 #[link_section = ".rwtext"]

diff --git a/esp-hal/src/time.rs b/esp-hal/src/time.rs
@@ -50,10 +50,10 @@ pub fn uptime() -> fugit::Instant<u64, 1, 1_000_000> {
 
 #[cfg(esp32)]
 pub(crate) fn time_init() {
-    let apb = Clocks::get().apb_clock.to_Hz();
+    let apb = crate::Clocks::get().apb_clock.to_Hz();
     // we assume 80MHz APB clock source - there is no way to configure it in a
     // different way currently
-    assert!(apb, 80_000_000u32);
+    assert_eq!(apb, 80_000_000u32);
 
     let tg0 = unsafe { crate::peripherals::TIMG0::steal() };