Improve QoR when threading models with SyncReadMems #639
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davidbiancolin
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sim/midas/src/main/scala/midas/passes/fame/ImplementThreadedSyncReadMems.scala
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* See chipsalliance/firrtl#1908 * Will revert this commit when change is available in FireSim
* Better BRAM/URAM inference in many cases for Vivado
* Implement threaded memory with monolithic BRAM + read data buffers * Substitute memories for ThreadedSyncReadMems in MuxingMultithreader * Separate generation of implementations into new ImplementThreadedSyncReadMems pass * Add pipelining to incorporate output FF option into BRAM
* Avoid issue of exposing custom IR nodes * Address PR review feedback
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Currently, synchronous-read memories get processed with
VerilogMemDelaysbefore FAME5 multi-threading, which leads to inconsistent BRAM inference and generally worse QoR. This PR fixes that by generating specialized implementations of natively multi-threaded synchronous-read memories. These implementations generally use RAM resources more effectively than the baseline unoptimized simulators.This also copies in the fix to
VerilogMemDelaysfrom chipsalliance/firrtl#1908. This fix can be reverted when the FIRRTL upstream changes make it to FireSim, but since that will take a while, it's good to get this bugfix in.