Update RENDER_SURFACE_STATE for Xe Hpc

For Xe Hp and later rename RSS tile mode enum from YMAJOR to TILE4 Related-To: NEO-6466 Signed-off-by: Mateusz Jablonski <[email protected]>
intel · Jan 24, 2022 · 0c933d8 · 0c933d8
1 parent e379249
commit 0c933d8
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Showing 8 changed files with 113 additions and 113 deletions.
diff --git a/level_zero/core/test/unit_tests/sources/kernel/test_kernel.cpp b/level_zero/core/test/unit_tests/sources/kernel/test_kernel.cpp
@@ -2331,7 +2331,7 @@ TEST_F(KernelImplicitArgTests, givenKernelWithoutImplicitArgsWhenPatchingImplici
 
 using MultiTileModuleTest = Test<MultiTileModuleFixture>;
 
-HWTEST2_F(MultiTileModuleTest, GivenMultiTileDeviceWhenSettingKernelArgAndSurfaceStateThenMultiTileFlagsAreSetCorrectly, isXeHpOrXeHpcCore) {
+HWTEST2_F(MultiTileModuleTest, GivenMultiTileDeviceWhenSettingKernelArgAndSurfaceStateThenMultiTileFlagsAreSetCorrectly, IsXeHpCore) {
     using RENDER_SURFACE_STATE = typename FamilyType::RENDER_SURFACE_STATE;
     ze_kernel_desc_t desc = {};
     desc.pKernelName = kernelName.c_str();

diff --git a/opencl/test/unit_test/mem_obj/image_set_arg_tests.cpp b/opencl/test/unit_test/mem_obj/image_set_arg_tests.cpp
@@ -265,6 +265,7 @@ HWTEST_F(ImageSetArgTest, givenImageArraySizeGreaterThanOneButTypeIsNotImageArra
 
     ClSurfaceFormatInfo surfaceFormatInfo{};
     surfaceFormatInfo.surfaceFormat.GMMSurfaceFormat = GMM_FORMAT_B8G8R8A8_UNORM;
+    surfaceFormatInfo.surfaceFormat.ImageElementSizeInBytes = 4u;
     imageInfo.surfaceFormat = &surfaceFormatInfo.surfaceFormat;
     cl_image_desc imageDesc = Image2dDefaults::imageDesc;
     imageDesc.image_array_size = 3u;

diff --git a/opencl/test/unit_test/mem_obj/nv12_image_tests.cpp b/opencl/test/unit_test/mem_obj/nv12_image_tests.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2021 Intel Corporation
+ * Copyright (C) 2018-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -421,7 +421,7 @@ HWTEST_F(Nv12ImageTest, WhenSettingImageArgUvPlaneImageThenOffsetSurfaceBaseAddr
 
     auto tileMode = RENDER_SURFACE_STATE::TILE_MODE_LINEAR;
     if (imageNV12->isTiledAllocation()) {
-        tileMode = RENDER_SURFACE_STATE::TILE_MODE_YMAJOR;
+        tileMode = static_cast<typename RENDER_SURFACE_STATE::TILE_MODE>(MockGmmResourceInfo::yMajorTileModeValue);
     }
 
     EXPECT_EQ(tileMode, surfaceState.getTileMode());

diff --git a/shared/source/generated/xe_hp_core/hw_cmds_generated_xe_hp_core.inl b/shared/source/generated/xe_hp_core/hw_cmds_generated_xe_hp_core.inl
@@ -1344,7 +1344,7 @@ typedef struct tagRENDER_SURFACE_STATE {
         TILE_MODE_LINEAR = 0x0,
         TILE_MODE_TILE64 = 0x1,
         TILE_MODE_XMAJOR = 0x2,
-        TILE_MODE_YMAJOR = 0x3, // patched - old name for TILE_MODE_TILE4
+        TILE_MODE_TILE4 = 0x3,
     } TILE_MODE;
     typedef enum tagSURFACE_HORIZONTAL_ALIGNMENT {
         SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_16 = 0x0,

diff --git a/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl b/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl
diff --git a/shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl b/shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl
@@ -1217,9 +1217,9 @@ typedef struct tagRENDER_SURFACE_STATE {
             uint32_t Reserved_252 : BITFIELD_RANGE(28, 29);
             uint32_t MemoryCompressionEnable : BITFIELD_RANGE(30, 30);
             uint32_t MemoryCompressionType : BITFIELD_RANGE(31, 31);
-            // DWORD 8
+            // DWORD 8, 9
             uint64_t SurfaceBaseAddress;
-            // DWORD 10
+            // DWORD 10, 11
             uint64_t QuiltWidth : BITFIELD_RANGE(0, 4);
             uint64_t QuiltHeight : BITFIELD_RANGE(5, 9);
             uint64_t ClearValueAddressEnable : BITFIELD_RANGE(10, 10);
@@ -1259,16 +1259,15 @@ typedef struct tagRENDER_SURFACE_STATE {
             uint32_t SeparateUvPlaneEnable : BITFIELD_RANGE(31, 31);
             // DWORD 7
             uint32_t Reserved_224;
-            // DWORD 8
+            // DWORD 8, 9
             uint64_t Reserved_256;
             // DWORD 10
-            uint64_t Reserved_320 : BITFIELD_RANGE(0, 11);
-            uint64_t Reserved_332 : 20; /* WARNING: Uncontinuous fields, bit position gap. Patched with dummy field */
+            uint64_t Reserved_320 : BITFIELD_RANGE(0, 31);
             // DWORD 11
             uint64_t YOffsetForVPlane : BITFIELD_RANGE(32, 45);
-            uint64_t Reserved_366 : 2; /* WARNING: Uncontinuous fields, bit position gap. Patched with dummy field */
+            uint64_t Reserved_366 : BITFIELD_RANGE(46, 47);
             uint64_t XOffsetForVPlane : BITFIELD_RANGE(48, 61);
-            uint64_t Reserved_382 : 2; /* WARNING: Uncontinuous fields, bit position gap. Patched with dummy field */
+            uint64_t Reserved_382 : BITFIELD_RANGE(62, 63);
             // DWORD 12
             uint32_t Reserved_384;
             // DWORD 13
@@ -1294,15 +1293,14 @@ typedef struct tagRENDER_SURFACE_STATE {
             // DWORD 6
             uint32_t AuxiliarySurfaceMode : BITFIELD_RANGE(0, 2);
             uint32_t AuxiliarySurfacePitch : BITFIELD_RANGE(3, 12);
-            uint32_t Reserved_205 : 1; /* WARNING: Uncontinuous fields, bit position gap. Patched with dummy field */
-            uint32_t Reserved_206 : BITFIELD_RANGE(14, 15);
+            uint32_t Reserved_205 : BITFIELD_RANGE(13, 15);
             uint32_t AuxiliarySurfaceQpitch : BITFIELD_RANGE(16, 30);
             uint32_t Reserved_223 : BITFIELD_RANGE(31, 31);
             // DWORD 7
             uint32_t Reserved_224;
-            // DWORD 8
+            // DWORD 8, 9
             uint64_t Reserved_256;
-            // DWORD 10
+            // DWORD 10, 11
             uint64_t Reserved_320;
             // DWORD 12
             uint32_t Reserved_384;
@@ -1330,9 +1328,9 @@ typedef struct tagRENDER_SURFACE_STATE {
             uint32_t Reserved_192;
             // DWORD 7
             uint32_t Reserved_224;
-            // DWORD 8
+            // DWORD 8, 9
             uint64_t Reserved_256;
-            // DWORD 10
+            // DWORD 10, 11
             uint64_t Reserved_320 : BITFIELD_RANGE(0, 11);
             uint64_t AuxiliarySurfaceBaseAddress : BITFIELD_RANGE(12, 63);
             // DWORD 12
@@ -1360,7 +1358,6 @@ typedef struct tagRENDER_SURFACE_STATE {
         TILE_MODE_TILE64 = 0x1,
         TILE_MODE_XMAJOR = 0x2,
         TILE_MODE_TILE4 = 0x3,
-        TILE_MODE_YMAJOR = 0x3, // patched - old name for TILE_MODE_TILE4
     } TILE_MODE;
     typedef enum tagSURFACE_HORIZONTAL_ALIGNMENT {
         SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_16 = 0x0,

diff --git a/shared/test/common/mocks/mock_gmm_resource_info.h b/shared/test/common/mocks/mock_gmm_resource_info.h
@@ -112,6 +112,7 @@ class MockGmmResourceInfo : public GmmResourceInfo {
     uint32_t cpuBltCalled = 0u;
     uint8_t cpuBltResult = 1u;
     static constexpr uint32_t getHAlignSurfaceStateResult = 2u;
+    static constexpr uint32_t yMajorTileModeValue = 3u;
 
   protected:
     MockGmmResourceInfo();

diff --git a/shared/test/common/mocks/mock_gmm_resource_info_common.cpp b/shared/test/common/mocks/mock_gmm_resource_info_common.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2020-2021 Intel Corporation
+ * Copyright (C) 2020-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -106,7 +106,7 @@ uint32_t MockGmmResourceInfo::getTileModeSurfaceState() {
 
     if (mockResourceCreateParams.Type == GMM_RESOURCE_TYPE::RESOURCE_2D ||
         mockResourceCreateParams.Type == GMM_RESOURCE_TYPE::RESOURCE_3D) {
-        return 3;
+        return yMajorTileModeValue;
     } else {
         return 0;
     }