corrections

README.md

@@ -1,14 +1,14 @@
-# LogicalNucleo
+# LogicAlNucleo
 
-A SUMP compatible Logical Analyser for the STM32F4 up to 10MSPS, 8Ch, 32K Samples memory.
+A SUMP compatible Logical Analyser for the NucleoF401RE (STM32F4xx) up to 10MSPS, 8Ch, 32K samples memory.
 
-This will turn any STM32F4 (may work with others) system into a Logical Analyser compatible with a subset of the SUMP protocol. It can be used with clients such as [PulseView](http://sigrok.org/wiki/PulseView), [sigrok-cli](http://sigrok.org/wiki/Sigrok-cli), and [LogicSniffer](http://www.lxtreme.nl/ols/). While it is not as feature complete as other products, such as the [OLS](http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer), it can turn that STM32 board that is lying around into a no frills, bare to the bones logic analyser.
+This will turn any NucleoF401RE (will work with others but it is not tested) system into a Logical Analyser compatible with a subset of the SUMP protocol. It can be used with clients such as [PulseView](http://sigrok.org/wiki/PulseView), [sigrok-cli](http://sigrok.org/wiki/Sigrok-cli), and [LogicSniffer](http://www.lxtreme.nl/ols/). While it is not as feature complete as other products, such as the [OLS](http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer), it can turn that STM32 board that is lying around into a no frills, bare to the bones, logic analyser.
 
 Sampling rate up to 500Khz should work on most platforms. Higher than that, only the F401RE, or other similar 84Mhz platform, should provide results with accurate timing measurements up to 10Mhz (probably near 20Mhz is achievable). If you wish to add support for other platforms, please focus in creating the appropriate unrolled loops. +150Mhz platforms can be easily supported as the more generic approach (wait_ns) can be used.
 
 PORTB is current used, and Pins PB_0 to PB_7 are reported. Unfortunately these pins are scattered over the board and are not contiguous. Check [this](http://developer.mbed.org/platforms/ST-Nucleo-F401RE/) diagram to find them.
 
-This implementation was based in the [mbed](https://mbed.org/) environment in order to increase its compatibility as new targets are expected to be supported. The focus of this implementation is compatibility and extensibility.
+This implementation was based in the [mbed](https://mbed.org/) environment in order to increase its compatibility, as new targets are expected to be supported. The focus of this implementation is compatibility and extensibility, and not only performance.
 
 ## Features
 
@@ -27,7 +27,7 @@ This implementation was based in the [mbed](https://mbed.org/) environment in or
 Just to prove it works and because screenshots are always nice.
 
 Channel 4 with a signal permanently set to 1, others set to 0.
-This capture was made using the test mode active. In this mode the board will provide a PWM signal in D9, with a period of 50us and pulse width of 20us. This pin was connected to D4 (PB_3) and sampled with great accuracy at 1Mhz.
+This capture was made using the test mode active. In this mode the board will provide a PWM signal in D9, with a period of 50us and pulse width of 20us (30us off). This pin was connected to D4 (PB_3) and sampled with great accuracy at 1Mhz.
 
 
 ![alt text](https://raw.githubusercontent.com/jpbarraca/LogicalNucleo/master/screenshots/screen1.png "LogicSniffer in Test Mode")