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[ExportVerilog] Wires are declared after they are referenced #438
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Will post a test case tomorrow. |
Thx, I appreciate it. I am not surprised that 'cyclic' graphs aren't handled properly yet but it should be straight-forward to fix. Thanks! |
emits
And while Verilator accepts it, Questa barfs:
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I was able to repro it without a cycle. |
* Gasket lower passes. The actual op emission yet to go. * Capnp message decode * Removing changes to RTL dialect * ExtractOp -> ArraySliceOp * Squashed commit of the following: commit b4f85eb Author: John Demme <[email protected]> Date: Tue Jan 5 11:51:51 2021 -0800 Adding support for structs commit 2692cb8 Merge: 5ff0abc b5240fa Author: John Demme <[email protected]> Date: Tue Jan 5 11:16:00 2021 -0800 Merge branch 'main' into rtl-reinterpret-cast commit 5ff0abc Author: John Demme <[email protected]> Date: Mon Jan 4 23:42:22 2021 -0800 No valid cast syntax which I could find commit 328941d Merge: 807fd58 e6a4b00 Author: John Demme <[email protected]> Date: Mon Jan 4 22:31:56 2021 -0800 Merge branch 'main' into rtl-reinterpret-cast commit 807fd58 Merge: 690fe48 463832b Author: John Demme <[email protected]> Date: Mon Jan 4 22:11:36 2021 -0800 Merge remote-tracking branch 'upstream/main' into rtl-reinterpret-cast commit 690fe48 Merge: fc0cddd a76e77d Author: John Demme <[email protected]> Date: Mon Jan 4 22:00:05 2021 -0800 Merge branch 'main' into rtl-reinterpret-cast commit fc0cddd Author: John Demme <[email protected]> Date: Mon Jan 4 18:58:10 2021 -0800 ExportVerilog support commit f361155 Author: John Demme <[email protected]> Date: Mon Jan 4 17:40:28 2021 -0800 Cast(To|From)Bits * Progress * ExportVerilog didn't support arrays on module ports * Revert "Squashed commit of the following:" This reverts commit ff35a6d. * Squashed commit of the following: commit 6641625 Author: John Demme <[email protected]> Date: Mon Jan 11 16:31:36 2021 -0800 Specify bit layout of types commit cd924d5 Author: John Demme <[email protected]> Date: Mon Jan 11 15:14:35 2021 -0800 Fixing test commit e45b6a1 Merge: f69c496 ce05aca Author: John Demme <[email protected]> Date: Mon Jan 11 15:11:03 2021 -0800 Merge branch 'main' into rtl-reinterpret-cast commit f69c496 Merge: eeb7dd4 ebaa869 Author: John Demme <[email protected]> Date: Mon Jan 11 15:10:45 2021 -0800 Merge branch 'main' into rtl-reinterpret-cast commit eeb7dd4 Merge: f5ee0f5 8f69a62 Author: John Demme <[email protected]> Date: Mon Jan 11 11:15:20 2021 -0800 Merge remote-tracking branch 'upstream/main' into rtl-reinterpret-cast commit f5ee0f5 Author: John Demme <[email protected]> Date: Sat Jan 9 19:43:49 2021 -0800 Changing back unrelated, spurious comment formatting commit 5abea84 Merge: b0b5cfa ad023e8 Author: John Demme <[email protected]> Date: Sat Jan 9 18:16:58 2021 -0800 Merge branch 'main' into rtl-reinterpret-cast commit b0b5cfa Author: John Demme <[email protected]> Date: Sat Jan 9 18:05:41 2021 -0800 I think this is everything except for the documentation. commit b4f85eb Author: John Demme <[email protected]> Date: Tue Jan 5 11:51:51 2021 -0800 Adding support for structs commit 2692cb8 Merge: 5ff0abc b5240fa Author: John Demme <[email protected]> Date: Tue Jan 5 11:16:00 2021 -0800 Merge branch 'main' into rtl-reinterpret-cast commit 5ff0abc Author: John Demme <[email protected]> Date: Mon Jan 4 23:42:22 2021 -0800 No valid cast syntax which I could find commit 328941d Merge: 807fd58 e6a4b00 Author: John Demme <[email protected]> Date: Mon Jan 4 22:31:56 2021 -0800 Merge branch 'main' into rtl-reinterpret-cast commit 807fd58 Merge: 690fe48 463832b Author: John Demme <[email protected]> Date: Mon Jan 4 22:11:36 2021 -0800 Merge remote-tracking branch 'upstream/main' into rtl-reinterpret-cast commit 690fe48 Merge: fc0cddd a76e77d Author: John Demme <[email protected]> Date: Mon Jan 4 22:00:05 2021 -0800 Merge branch 'main' into rtl-reinterpret-cast commit fc0cddd Author: John Demme <[email protected]> Date: Mon Jan 4 18:58:10 2021 -0800 ExportVerilog support commit f361155 Author: John Demme <[email protected]> Date: Mon Jan 4 17:40:28 2021 -0800 Cast(To|From)Bits * Decoder compiling * Decode module working * Decode cleanup * Encoder done! * Mitigation for #438 * Adding some names and adding a test * Making the test a bit more flexible * Remove rationale update * Cleanup and non-capnp build fixes * Clang-format * Feedback from Mike
Can you share a small testcase? I assume this is just when the operations are out of order? |
This emits out of line declations in the narrow case where we need to avoid verilog use-before-def issues.
Fixed in 20eefde |
In the situation where an expression cannot be inlined and appears in the IR after its use, ExportVerilog will emit the use before the declaration. Generally speaking, this will likely occur when a cycle occurs.
Setting
emitInlineWireDecls
(here) to false mitigates the issue. Always putting the wire declarations at the beginning of the file is the simplest thing to do, but probably not what we want.Should we set
emitInlineWireDecls
to false and treat optimal decl placement as a future cleanup/enhancement?The text was updated successfully, but these errors were encountered: