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[PowerPC] Switch to by-name matching for instructions (part 1 of 2).
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This is a follow-on to https://reviews.llvm.org/D134073.

After https://reviews.llvm.org/D137653 we can now switch the PPC
target away from positional operand matching.

This patch fixes all of the "easy" cases. While this changes a large
number of lines of tablegen source, it results in only a single
non-comment change in the code generated by tablegen: the (unused)
codegen-only "MTVRSAVEv" instruction was previously incorrectly
encoding operand 0, and now encodes (correctly) operand 1.

Changes which result in generated-code changes have been split off
into the next (smaller) patch, for ease of review.

Reviewed By: barannikov88

Differential Revision: https://reviews.llvm.org/D137661
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jyknight committed Feb 2, 2023
1 parent 9fe7d38 commit 4b43ef3
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Showing 11 changed files with 2,769 additions and 2,751 deletions.
1,110 changes: 555 additions & 555 deletions llvm/lib/Target/PowerPC/PPCInstr64Bit.td

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936 changes: 468 additions & 468 deletions llvm/lib/Target/PowerPC/PPCInstrAltivec.td

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341 changes: 174 additions & 167 deletions llvm/lib/Target/PowerPC/PPCInstrFormats.td

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32 changes: 16 additions & 16 deletions llvm/lib/Target/PowerPC/PPCInstrFuture.td
Original file line number Diff line number Diff line change
Expand Up @@ -53,36 +53,36 @@ let Predicates = [IsISAFuture] in {

let Predicates = [HasVSX, IsISAFuture] in {
let mayLoad = 1 in {
def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
"lxvrl $XT, $src, $rB", IIC_LdStLoad, []>;
def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
"lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;

def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
"lxvrll $XT, $src, $rB", IIC_LdStLoad, []>;
def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
"lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;

def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp),
(ins memr:$src, g8rc:$rB),
"lxvprl $XTp, $src, $rB", IIC_LdStLFD, []>;
(ins memr:$RA, g8rc:$RB),
"lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;

def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp),
(ins memr:$src, g8rc:$rB),
"lxvprll $XTp, $src, $rB", IIC_LdStLFD, []>;
(ins memr:$RA, g8rc:$RB),
"lxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
}

let mayStore = 1 in {
def STXVRL : XX1Form_memOp<31, 653, (outs),
(ins vsrc:$XT, memr:$dst, g8rc:$rB),
"stxvrl $XT, $dst, $rB", IIC_LdStLoad, []>;
(ins vsrc:$XT, memr:$RA, g8rc:$RB),
"stxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;

def STXVRLL : XX1Form_memOp<31, 685, (outs),
(ins vsrc:$XT, memr:$dst, g8rc:$rB),
"stxvrll $XT, $dst, $rB", IIC_LdStLoad, []>;
(ins vsrc:$XT, memr:$RA, g8rc:$RB),
"stxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;

def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs),
(ins vsrprc:$XTp, memr:$src, g8rc:$rB),
"stxvprl $XTp, $src, $rB", IIC_LdStLFD, []>;
(ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
"stxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;

def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs),
(ins vsrprc:$XTp, memr:$src, g8rc:$rB),
"stxvprll $XTp, $src, $rB", IIC_LdStLFD, []>;
(ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
"stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
}
}
28 changes: 14 additions & 14 deletions llvm/lib/Target/PowerPC/PPCInstrHTM.td
Original file line number Diff line number Diff line change
Expand Up @@ -35,50 +35,50 @@ def TEND : XForm_htm1 <31, 686,
(outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR>;

def TABORT : XForm_base_r3xo <31, 910,
(outs), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR,
(outs), (ins gprc:$RA), "tabort. $RA", IIC_SprMTSPR,
[]>, isRecordForm {
let RST = 0;
let B = 0;
let RB = 0;
}

def TABORTWC : XForm_base_r3xo <31, 782,
(outs), (ins u5imm:$RTS, gprc:$A, gprc:$B),
"tabortwc. $RTS, $A, $B", IIC_SprMTSPR, []>,
(outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
"tabortwc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
isRecordForm;

def TABORTWCI : XForm_base_r3xo <31, 846,
(outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B),
"tabortwci. $RTS, $A, $B", IIC_SprMTSPR, []>,
(outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
"tabortwci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
isRecordForm;

def TABORTDC : XForm_base_r3xo <31, 814,
(outs), (ins u5imm:$RTS, gprc:$A, gprc:$B),
"tabortdc. $RTS, $A, $B", IIC_SprMTSPR, []>,
(outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
"tabortdc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
isRecordForm;

def TABORTDCI : XForm_base_r3xo <31, 878,
(outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B),
"tabortdci. $RTS, $A, $B", IIC_SprMTSPR, []>,
(outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
"tabortdci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
isRecordForm;

def TSR : XForm_htm2 <31, 750,
(outs), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR>,
isRecordForm;

def TRECLAIM : XForm_base_r3xo <31, 942,
(outs), (ins gprc:$A), "treclaim. $A",
(outs), (ins gprc:$RA), "treclaim. $RA",
IIC_SprMTSPR, []>,
isRecordForm {
let RST = 0;
let B = 0;
let RB = 0;
}

def TRECHKPT : XForm_base_r3xo <31, 1006,
(outs), (ins), "trechkpt.", IIC_SprMTSPR, []>,
isRecordForm {
let RST = 0;
let A = 0;
let B = 0;
let RA = 0;
let RB = 0;
}

}
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