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[ac_range_check/dv] Create initial DV environment #6039

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[ac_range_check/dv] Create initial DV environment

[ac_range_check/dv] Create initial DV environment #6039

Triggered via pull request February 14, 2025 14:59
@martin-velaymartin-velay
synchronize #26267
martin-velay:acrc_init
Status Failure
Total duration 3m 43s
Artifacts –

ci.yml

on: pull_request
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3m 1s
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Earl Grey for CW310 Hyperdebug  /  Build bitstream
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310  /  Build bitstream
Earl Grey for CW310 / Build bitstream
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0s
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Build documentation
0s
Build documentation
Airgapped build
0s
Airgapped build
Verible lint
0s
Verible lint
Run OTBN smoke Test
0s
Run OTBN smoke Test
Run OTBN crypto tests
0s
Run OTBN crypto tests
Verilated English Breakfast
0s
Verilated English Breakfast
Verilated Earl Grey
0s
Verilated Earl Grey
CW305's Bitstream
0s
CW305's Bitstream
Build Docker Containers
0s
Build Docker Containers
Build and test software
0s
Build and test software
Build and test Darjeeling software
0s
Build and test Darjeeling software
QEMU smoketest
0s
QEMU smoketest
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
Hyper310 ROM_EXT Tests  /  FPGA test
Hyper310 ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
24s
Verify FPGA jobs
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4 errors
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Link Check failed.
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Process completed with exit code 1.
Verify FPGA jobs
Process completed with exit code 1.
Verify FPGA jobs
Process completed with exit code 1.